Date: Tue, 21 Nov 2017 09:52:34 -0700 From: Warner Losh <imp@bsdimp.com> To: Bruce Evans <brde@optusnet.com.au> Cc: Warner Losh <imp@freebsd.org>, src-committers <src-committers@freebsd.org>, "svn-src-all@freebsd.org" <svn-src-all@freebsd.org>, "svn-src-head@freebsd.org" <svn-src-head@freebsd.org> Subject: Re: svn commit: r326037 - head/share/mk Message-ID: <CANCZdfotGJCm7UQgtmoUB-=sWD65n0GkpYz=DLeVoDb=uyc5TQ@mail.gmail.com> In-Reply-To: <20171121233000.M2067@besplex.bde.org> References: <201711202241.vAKMfMpO008434@repo.freebsd.org> <20171121233000.M2067@besplex.bde.org>
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On Tue, Nov 21, 2017 at 5:44 AM, Bruce Evans <brde@optusnet.com.au> wrote: > On Mon, 20 Nov 2017, Warner Losh wrote: > > Author: imp >> Date: Mon Nov 20 22:41:22 2017 >> New Revision: 326037 >> URL: https://svnweb.freebsd.org/changeset/base/326037 >> >> Log: >> Add -mno-avx2 for clang as well as -mno-avx. We don't want either of >> them when asking for no SIMD. >> > > Is this needed. For SSE, -mno-sse implies -mno-sse[2,3,4,...] so > an multiple set of no-sse* flags are not needed (I have only checked this > for sse2). Multiple no-sse* flags are also not used. I've had reports that the EFI boot loader uses these AVX2 instructions when you set CPUTYPE=haswell. I've not independently confirmed this, as this was a few years ago. But it was an easy bug to fix. Modified: head/share/mk/bsd.cpu.mk >> ============================================================ >> ================== >> --- head/share/mk/bsd.cpu.mk Mon Nov 20 22:27:33 2017 (r326036) >> +++ head/share/mk/bsd.cpu.mk Mon Nov 20 22:41:22 2017 (r326037) >> @@ -393,7 +393,7 @@ CFLAGS += ${_CPUCFLAGS} >> # (-mfpmath= is not supported) >> # >> .if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64" >> -CFLAGS_NO_SIMD.clang= -mno-avx >> +CFLAGS_NO_SIMD.clang= -mno-avx -mno-avx2 >> CFLAGS_NO_SIMD= -mno-mmx -mno-sse >> > > Nearby example of non-use for SSE. Yes. .endif >> CFLAGS_NO_SIMD += ${CFLAGS_NO_SIMD.${COMPILER_TYPE}} >> > > Testing shows that -mavx2 -mno-avx kills all AVX for clang in an example > that only generates AVX instructions (-mavx2 enabls these as a subset). I'll have to confirm. Skylake adds avx512 as well, so I'll have to check it there too... Warner
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