Date: Wed, 9 May 2007 00:23:21 GMT From: Bruce M Simpson <bms@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 119532 for review Message-ID: <200705090023.l490NLLV090384@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=119532 Change 119532 by bms@bms_anglepoise on 2007/05/09 00:22:58 siba(4) is now able to enumerate the bus on the Broadcom Sentry5; newbus child attachments to come. Affected files ... .. //depot/projects/mips2/src/sys/mips/mips32/sentry5/siba.c#2 edit .. //depot/projects/mips2/src/sys/mips/mips32/sentry5/siba_ids.h#1 add .. //depot/projects/mips2/src/sys/mips/mips32/sentry5/sibareg.h#1 add .. //depot/projects/mips2/src/sys/mips/mips32/sentry5/sibavar.h#1 add Differences ... ==== //depot/projects/mips2/src/sys/mips/mips32/sentry5/siba.c#2 (text+ko) ==== @@ -1,3 +1,29 @@ +/*- + * Copyright (c) 2007 Bruce M. Simpson. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); @@ -12,75 +38,314 @@ #include <machine/bus.h> #include <mips/mips32/sentry5/sibavar.h> -#include <mips/mips32/sentry5/sentry5reg.h> +#include <mips/mips32/sentry5/sibareg.h> +#include <mips/mips32/sentry5/siba_ids.h> + +/* + * TODO: cpu clock calculation. + * TODO: De-mipsify this code. + * TODO: Move siba to a machine independent location. + * TODO: Attempt to attach the children. + * TODO: resource manager for children (proxy it to nexus) + * TODO: Put the information into ivars like PCI does. + * TODO: Support detach. + * TODO: Power management. + * TODO: code cleanup. + * TODO: Support deployments of siba other than as a system bus. + */ + +#ifndef MIPS_MEM_RID +#define MIPS_MEM_RID 0x20 +#endif + +static int siba_debug = 1; +static const char descfmt[] = "Sonics SiliconBackplane rev %s"; +#define SIBA_DEVDESCLEN sizeof(descfmt) + 8 + +/* + * Device identifiers and descriptions. + */ +static struct siba_devid siba_devids[] = { + { SIBA_VID_BROADCOM, SIBA_DEVID_CHIPCOMMON, SIBA_REV_ANY, + "ChipCommon" }, + { SIBA_VID_BROADCOM, SIBA_DEVID_SDRAM, SIBA_REV_ANY, + "SDRAM controller" }, + { SIBA_VID_BROADCOM, SIBA_DEVID_PCI, SIBA_REV_ANY, + "PCI host interface" }, + { SIBA_VID_BROADCOM, SIBA_DEVID_MIPS, SIBA_REV_ANY, + "MIPS core" }, + { SIBA_VID_BROADCOM, SIBA_DEVID_ETHERNET, SIBA_REV_ANY, + "Ethernet core" }, + { SIBA_VID_BROADCOM, SIBA_DEVID_USB, SIBA_REV_ANY, + "USB host controller" }, + { SIBA_VID_BROADCOM, SIBA_DEVID_IPSEC, SIBA_REV_ANY, + "IPSEC accelerator" }, + { SIBA_VID_BROADCOM, SIBA_DEVID_SDRAMDDR, SIBA_REV_ANY, + "SDRAM/DDR controller" }, + { SIBA_VID_BROADCOM, SIBA_DEVID_MIPS_3302, SIBA_REV_ANY, + "MIPS 3302 core" }, + { 0, 0, 0, NULL } +}; static int siba_activate_resource(device_t, device_t, int, int, struct resource *); +static device_t siba_add_child(device_t, int, const char *, int); static struct resource * siba_alloc_resource(device_t, device_t, int, int *, u_long, u_long, u_long, u_int); static int siba_attach(device_t); -static int siba_detach(device_t); -//static int siba_identify(driver_t *, device_t); +static void siba_destroy_devinfo(struct siba_devinfo *); +static struct siba_devid * + siba_dev_match(uint16_t, uint16_t, uint8_t); +static uint8_t siba_getncores(uint16_t); static int siba_print_child(device_t, device_t); static int siba_probe(device_t); +static struct siba_devinfo * + siba_setup_devinfo(device_t, uint8_t); -static int -siba_probe(device_t dev) +/* + * Earlier ChipCommon revisions have hardcoded number of cores + * present dependent on the ChipCommon ID. + */ +static uint8_t +siba_getncores(uint16_t ccid) { + uint8_t ncores; + + switch (ccid) { + case SIBA_CCID_SENTRY5: + ncores = 7; + break; + case SIBA_CCID_BCM4710: + case SIBA_CCID_BCM4704: + ncores = 9; + break; + default: + ncores = 0; + } - printf("%s: entry\n", __func__); - device_set_desc(dev, "Sonics SiliconBackplane"); - return (0); + return (ncores); } static int -siba_attach(device_t dev) +siba_probe(device_t dev) { struct siba_softc *sc = device_get_softc(dev); + uint32_t idlo, idhi; + uint16_t ccid; int rid; - printf("%s: entry\n", __func__); sc->sc_dev = dev; - rid = 0x20; /* XXX MIPS_MEM_RID */ + /* + * Map the ChipCommon register set using the hints the kernel + * was compiled with. + */ + rid = MIPS_MEM_RID; sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->sc_mem == NULL) { - device_printf(dev, "unable to allocate memory resource\n"); + device_printf(dev, "unable to allocate probe aperture\n"); + return (ENXIO); + } + sc->sc_bt = rman_get_bustag(sc->sc_mem); + sc->sc_bh = rman_get_bushandle(sc->sc_mem); + sc->sc_maddr = rman_get_start(sc->sc_mem); + sc->sc_msize = rman_get_size(sc->sc_mem); + + if (siba_debug) { + device_printf(dev, "start %08x len %08x\n", + sc->sc_maddr, sc->sc_msize); + } + + idlo = siba_read_4(sc, 0, SIBA_CORE_IDLO); + idhi = siba_read_4(sc, 0, SIBA_CORE_IDHI); + ccid = ((idhi & 0x8ff0) >> 4); + if (siba_debug) { + device_printf(dev, "idlo = %08x\n", idlo); + device_printf(dev, "idhi = %08x\n", idhi); + device_printf(dev, " chipcore id = %08x\n", ccid); + } + + /* + * For now, check that the first core is the ChipCommon core. + */ + if (ccid != SIBA_DEVID_CHIPCOMMON) { + if (siba_debug) + device_printf(dev, "first core is not ChipCommon\n"); + return (ENXIO); + } + + /* + * Determine backplane revision and set description string. + */ + uint32_t rev; + char *revp; + char descbuf[SIBA_DEVDESCLEN]; + + rev = idlo & 0xF0000000; + revp = "unknown"; + if (rev == 0x00000000) + revp = "2.2"; + else if (rev == 0x10000000) + revp = "2.3"; + + (void)snprintf(descbuf, sizeof(descbuf), descfmt, revp); + device_set_desc_copy(dev, descbuf); + + /* + * Determine how many cores are present on this siba bus, so + * that we may map them all. + */ + uint32_t ccidreg; + uint16_t cc_id; + uint16_t cc_rev; + + ccidreg = siba_read_4(sc, 0, SIBA_CC_CCID); + cc_id = (ccidreg & SIBA_CC_IDMASK); + cc_rev = (ccidreg & SIBA_CC_REVMASK) >> SIBA_CC_REVSHIFT; + if (siba_debug) { + device_printf(dev, "ccid = %08x, cc_id = %04x, cc_rev = %04x\n", + ccidreg, cc_id, cc_rev); + } + + sc->sc_ncores = siba_getncores(cc_id); + if (siba_debug) { + device_printf(dev, "%d cores detected.\n", sc->sc_ncores); + } + + /* + * Now we know how many cores are on this siba, release the + * mapping and allocate a new mapping spanning all cores on the bus. + */ + rid = MIPS_MEM_RID; + int result; + result = bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->sc_mem); + if (result != 0) { + device_printf(dev, "error %d releasing resource\n", result); return (ENXIO); } - device_printf(dev, "%s: start %p len %ld\n", __func__, - (void *)(intptr_t)rman_get_start(sc->sc_mem), - rman_get_size(sc->sc_mem)); + uint32_t total; + total = sc->sc_ncores * SIBA_CORE_LEN; - /* XXX: TODO: Check it is a SIBA */ + sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, + sc->sc_maddr, sc->sc_maddr + total - 1, total, RF_ACTIVE); + if (sc->sc_mem == NULL) { + device_printf(dev, "unable to allocate entire aperture\n"); + return (ENXIO); + } + sc->sc_bt = rman_get_bustag(sc->sc_mem); + sc->sc_bh = rman_get_bushandle(sc->sc_mem); + sc->sc_maddr = rman_get_start(sc->sc_mem); + sc->sc_msize = rman_get_size(sc->sc_mem); - /* Probe for and attach children. */ - bus_generic_probe(dev); - bus_generic_attach(dev); + if (siba_debug) { + device_printf(dev, "after remapping: start %08x len %08x\n", + sc->sc_maddr, sc->sc_msize); + } + bus_set_resource(dev, SYS_RES_MEMORY, rid, sc->sc_maddr, sc->sc_msize); return (0); } static int -siba_detach(device_t dev) +siba_attach(device_t dev) { + struct siba_softc *sc = device_get_softc(dev); + uint32_t idlo, idhi; + uint16_t ccid; + uint32_t rev; + + if (siba_debug) + printf("%s: entry\n", __func__); + + bus_generic_probe(dev); + + /* + * Now that all bus space is mapped and visible to the CPU, + * enumerate its children. + * Note that only one core may be mapped at any time if the siba + * bus is the child of a PCI or PCMCIA bus. + */ + uint16_t vendorid; + int idx; + + for (idx = 0; idx < sc->sc_ncores; idx++) { + struct siba_devid *sd; + + idlo = siba_read_4(sc, idx, SIBA_CORE_IDLO); + idhi = siba_read_4(sc, idx, SIBA_CORE_IDHI); + ccid = ((idhi & 0x8ff0) >> 4); + vendorid = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT; + rev = (idhi & SSB_IDHIGH_RCLO); + rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT; + + struct siba_devinfo *sdi; + + sdi = siba_setup_devinfo(NULL, 0); + sdi->sdi_vid = vendorid; + sdi->sdi_devid = ccid; + sdi->sdi_rev = rev; + sdi->sdi_idx = idx; + sdi->sdi_irq = 0; /* XXX notyet */ + + sd = siba_dev_match(vendorid, ccid, rev); + if (sd != NULL) { + device_printf(dev, "core %d: %s rev %02x\n", + idx, sd->sd_desc, rev); + } else { + device_printf(dev, + "core %d: vid %04x pid %04x rev %02x\n", + idx, vendorid, ccid, rev); + } - printf("%s: entry\n", __func__); - return (ENXIO); + /* + * Try to attach the child. + * We need to set resources for the child from here; + * drivers which attach to siba will need to use the + * instance variables like children of pcib do. + */ + device_t child; + child = device_add_child(dev, NULL, -1); + if (child == NULL) { + device_printf(dev, "could not add child\n"); + siba_destroy_devinfo(sdi); + } else { + device_printf(dev, "child is %p\n", child); + device_set_ivars(child, sdi); + #ifdef notyet + bus_addr_t baseaddr; + baseaddr = sc->sc_maddr + (idx * SIBA_CORE_LEN); + bus_set_resource(child, SYS_RES_MEMORY, MIPS_MEM_RID, + baseaddr, baseaddr + SIBA_CORE_LEN - 1); + #endif + } + } + + return (bus_generic_attach(dev)); } -#if 0 -static int -siba_identify(driver_t *drv, device_t parent) +static struct siba_devid * +siba_dev_match(uint16_t vid, uint16_t devid, uint8_t rev) { + size_t i, bound; + struct siba_devid *sd; + + bound = sizeof(siba_devids) / sizeof(struct siba_devid); + sd = &siba_devids[0]; + for (i = 0; i < bound; i++, sd++) { + if (((vid == SIBA_VID_ANY) || (vid == sd->sd_vendor)) && + ((devid == SIBA_DEVID_ANY) || (devid == sd->sd_device)) && + ((rev == SIBA_REV_ANY) || (rev == sd->sd_rev) || + (sd->sd_rev == SIBA_REV_ANY))) + break; + } + if (i == bound) + sd = NULL; - printf("%s: entry\n", __func__); - return (ENXIO); + return (sd); } -#endif static int siba_print_child(device_t bus, device_t child) @@ -98,7 +363,9 @@ u_long start, u_long end, u_long count, u_int flags) { - printf("%s: entry\n", __func__); + if (siba_debug) + printf("%s: entry\n", __func__); + return (NULL); } @@ -107,25 +374,69 @@ struct resource *r) { - printf("%s: entry\n", __func__); + if (siba_debug) + printf("%s: entry\n", __func__); + return (ENXIO); } +static struct siba_devinfo * +siba_setup_devinfo(device_t dev, uint8_t idx) +{ + struct siba_devinfo *sdi; + + sdi = malloc(sizeof(*sdi), M_DEVBUF, M_WAITOK | M_ZERO); + resource_list_init(&sdi->sdi_rl); + + return (sdi); +} + +static void +siba_destroy_devinfo(struct siba_devinfo *sdi) +{ + + resource_list_free(&sdi->sdi_rl); + free(sdi, M_DEVBUF); +} + +static device_t +siba_add_child(device_t dev, int order, const char *name, int unit) +{ +#if 1 + + device_printf(dev, "%s: entry\n", __func__); + return (NULL); +#else + device_t child; + struct siba_devinfo *sdi; + + child = device_add_child_ordered(dev, order, name, unit); + if (child == NULL) + return (NULL); + + sdi = malloc(sizeof(struct siba_devinfo), M_DEVBUF, M_NOWAIT|M_ZERO); + if (sdi == NULL) + return (NULL); + + device_set_ivars(child, sdi); + return (child); +#endif +} + static device_method_t siba_methods[] = { /* Device interface */ - //DEVMETHOD(device_identify, siba_identify), - DEVMETHOD(device_probe, siba_probe), DEVMETHOD(device_attach, siba_attach), - DEVMETHOD(device_detach, siba_detach), DEVMETHOD(device_detach, bus_generic_detach), + DEVMETHOD(device_probe, siba_probe), + DEVMETHOD(device_resume, bus_generic_resume), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, bus_generic_suspend), - DEVMETHOD(device_resume, bus_generic_resume), /* Bus interface */ + DEVMETHOD(bus_activate_resource,siba_activate_resource), + DEVMETHOD(bus_add_child, siba_add_child), + DEVMETHOD(bus_alloc_resource, siba_alloc_resource), DEVMETHOD(bus_print_child, siba_print_child), - DEVMETHOD(bus_alloc_resource, siba_alloc_resource), - DEVMETHOD(bus_activate_resource,siba_activate_resource), DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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