From owner-freebsd-arm@FreeBSD.ORG Tue Dec 29 20:46:50 2009 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id BF2C51065695 for ; Tue, 29 Dec 2009 20:46:50 +0000 (UTC) (envelope-from tinguely@casselton.net) Received: from casselton.net (casselton.net [63.165.140.2]) by mx1.freebsd.org (Postfix) with ESMTP id 7D0998FC16 for ; Tue, 29 Dec 2009 20:46:50 +0000 (UTC) Received: from casselton.net (localhost [127.0.0.1]) by casselton.net (8.14.3/8.14.3) with ESMTP id nBTKknr5076661 for ; Tue, 29 Dec 2009 14:46:49 -0600 (CST) (envelope-from tinguely@casselton.net) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=casselton.net; s=ccnMail; t=1262119609; bh=Tcue6lC1htJMmuObILjc42Ww9jn+PswXq8F8gPEr5N4=; h=Date:From:Message-Id:To:Subject; b=WhgjLE+vuesRD6QFMRsaxOiJWwkch1E17xkxHdEquh2xymPbOxCzK5kVsUdCnHAq7 yE8Mu8xsVUPM2BsFlk2fsLXSm3YXYTPvTawvxzaXdw27dQyU1c2x3JmaLCv+xjpz71 2Yug5boDm2WEyYyU6GZFWduoRfP46EgV5DSYeuGA= Received: (from tinguely@localhost) by casselton.net (8.14.3/8.14.2/Submit) id nBTKknjI076659 for freebsd-arm@freebsd.org; Tue, 29 Dec 2009 14:46:49 -0600 (CST) (envelope-from tinguely) Date: Tue, 29 Dec 2009 14:46:49 -0600 (CST) From: Mark Tinguely Message-Id: <200912292046.nBTKknjI076659@casselton.net> To: freebsd-arm@freebsd.org X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.3.2 (casselton.net [127.0.0.1]); Tue, 29 Dec 2009 14:46:49 -0600 (CST) Subject: cpu_throw()/cpu_switch() and L2 X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Dec 2009 20:46:50 -0000 FYI esp Sheeva users with corruption issues: I was looking at my new swtch.S routine and noticed that cpu_throw() and cpu_switch() do not wbinv the level 2 cache. For the majority of the ARMv5 processors this does not do anything. This could effect the Sheeva. Looking at the Sheeva "setttb" routine, wbinv both level 1 and level 2 caches, which it needs to to if the level 2 cache is virtually indexed. In my opinion, we should remove the l2 cache operation calls because if an architecture uses a virtual indexed level 2 caches, then the level cache will need to wb/inv everytime the level 1 cache is wb/inv; It makes more sense to me to do them together. One advantage is we would not miss cache flushing situation like the ones above. The caches in the newer architectures are PIPT, and don't need to be flushed for context changes, and pages sharing, etc. --Mark.