Skip site navigation (1)Skip section navigation (2)
Date:      Sat, 12 Mar 2005 08:05:03 +0000
From:      David Malone <>
To:        Daniel Eriksson <>
Cc:        'FreeBSD Current' <>
Subject:   Re: Higher interrupt rate after recent SMP/APIC timer changes?
Message-ID:  <>
In-Reply-To: <!~!>
References:  <!~!>

Next in thread | Previous in thread | Raw E-Mail | Index | Archive | Help
On Fri, Mar 11, 2005 at 11:51:40PM +0100, Daniel Eriksson wrote:
> This is an SMP box (dual AMD AthlonMP) running with HZ=2000 and POLLING
> enabled. Should I worry about the 4k intr/sec reported for lapic0 and
> lapic1, or is this the way things should be?

I believe this is what you should expect. The when using the lapic
for timers, the lapic is programmed to interrupt at HZ*2 and then
other timers are generated. See the commit messages for version
1.14 and 1.13 at:

for more details. (There is also one lapic per processor - previously
one timer interrupt would happen and then the processer that handeled
that interrupt would have to forward it to other processors.)


Want to link to this message? Use this URL: <>