From owner-svn-src-all@FreeBSD.ORG Wed Oct 16 02:46:01 2013 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 88D2C92F; Wed, 16 Oct 2013 02:46:01 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 749AD28F1; Wed, 16 Oct 2013 02:46:01 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id r9G2k1hx092614; Wed, 16 Oct 2013 02:46:01 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id r9G2k1Yq092613; Wed, 16 Oct 2013 02:46:01 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201310160246.r9G2k1Yq092613@svn.freebsd.org> From: Adrian Chadd Date: Wed, 16 Oct 2013 02:46:01 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r256573 - head/sys/mips/atheros X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Oct 2013 02:46:01 -0000 Author: adrian Date: Wed Oct 16 02:46:00 2013 New Revision: 256573 URL: http://svnweb.freebsd.org/changeset/base/256573 Log: Add in a write barrier after each if_arge write. Without correct barriers, this code just plain doesn't work on the mips74k cores (specifically the AR9344.) In particular, the MDIO register accesses need this barriering or MII bus access results in out-of-order garbage. Tested: * AR9344 (mips74k) * AR9331 (mips24k) Modified: head/sys/mips/atheros/if_argevar.h Modified: head/sys/mips/atheros/if_argevar.h ============================================================================== --- head/sys/mips/atheros/if_argevar.h Wed Oct 16 02:10:35 2013 (r256572) +++ head/sys/mips/atheros/if_argevar.h Wed Oct 16 02:46:00 2013 (r256573) @@ -55,10 +55,17 @@ /* * register space access macros */ +#define ARGE_BARRIER_READ(sc) bus_barrier(sc->arge_res, 0, 0, \ + BUS_SPACE_BARRIER_READ) +#define ARGE_BARRIER_WRITE(sc) bus_barrier(sc->arge_res, 0, 0, \ + BUS_SPACE_BARRIER_WRITE) +#define ARGE_BARRIER_RW(sc) bus_barrier(sc->arge_res, 0, 0, \ + BUS_SPACE_BARRIER_READ | \ + BUS_SPACE_BARRIER_WRITE) #define ARGE_WRITE(sc, reg, val) do { \ bus_write_4(sc->arge_res, (reg), (val)); \ + ARGE_BARRIER_WRITE((sc)); \ } while (0) - #define ARGE_READ(sc, reg) bus_read_4(sc->arge_res, (reg)) #define ARGE_SET_BITS(sc, reg, bits) \ @@ -71,6 +78,9 @@ ARGE_WRITE((_sc), (_reg), (_val)) #define ARGE_MDIO_READ(_sc, _reg) \ ARGE_READ((_sc), (_reg)) +#define ARGE_MDIO_BARRIER_READ(_sc) ARGE_BARRIER_READ(_sc) +#define ARGE_MDIO_BARRIER_WRITE(_sc) ARGE_BARRIER_WRITE(_sc) +#define ARGE_MDIO_BARRIER_RW(_sc) ARGE_BARRIER_READ_RW(_sc) #define ARGE_DESC_EMPTY (1 << 31) #define ARGE_DESC_MORE (1 << 24)