From owner-freebsd-amd64@FreeBSD.ORG Tue Jul 17 15:27:38 2012 Return-Path: Delivered-To: freebsd-amd64@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 90BAE106564A for ; Tue, 17 Jul 2012 15:27:38 +0000 (UTC) (envelope-from brde@optusnet.com.au) Received: from mail09.syd.optusnet.com.au (mail09.syd.optusnet.com.au [211.29.132.190]) by mx1.freebsd.org (Postfix) with ESMTP id 0DEA58FC0C for ; Tue, 17 Jul 2012 15:27:37 +0000 (UTC) Received: from c122-106-171-246.carlnfd1.nsw.optusnet.com.au (c122-106-171-246.carlnfd1.nsw.optusnet.com.au [122.106.171.246]) by mail09.syd.optusnet.com.au (8.13.1/8.13.1) with ESMTP id q6HFRTP6025993 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 18 Jul 2012 01:27:30 +1000 Date: Wed, 18 Jul 2012 01:27:29 +1000 (EST) From: Bruce Evans X-X-Sender: bde@besplex.bde.org To: Bruce Evans In-Reply-To: <20120717235622.C7417@besplex.bde.org> Message-ID: <20120718011942.D7642@besplex.bde.org> References: <201207171350.q6HDoAJS033797@freefall.freebsd.org> <20120717235622.C7417@besplex.bde.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Cc: freebsd-amd64@FreeBSD.org Subject: Re: amd64/169927: siginfo, si_code for fpe errors when error occurs using the SSE math processor X-BeenThere: freebsd-amd64@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the AMD64 platform List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Jul 2012 15:27:38 -0000 On Wed, 18 Jul 2012, Bruce Evans wrote: > On Tue, 17 Jul 2012, Konstantin Belousov wrote: >> ... >> + status =3D mxcsr & 0x3f; >> + control =3D (mxcsr >> 16) & 0x3f; >> + return (fpetable[status & (~control | 0x40)]); > > The 0x40 bit doesn't exist in the mxcsr status and ORing it in here has > no effect. Replace the last 3 lines by: > > return (fpetable[(status & (control >> 16)) & 0x3f]; Change status and control to mxcsr here, and remove the status and control variables. > .. > So I still want a single kernel exception handle that merges the statuses. Merge the independent statuses modified by their independent controls: return (fpetable[(fpsw & ((~fpcw & 0x3f) | 0x40)) | ((mxcsr & (mxcsr >> 16)) & 0x3f)]); Use the same trap handler that reads all these statuses and controls. Bruce