From owner-svn-src-head@FreeBSD.ORG Thu Dec 5 15:15:01 2013 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id A3B288AB; Thu, 5 Dec 2013 15:15:01 +0000 (UTC) Received: from bigwig.baldwin.cx (bigwig.baldwin.cx [IPv6:2001:470:1f11:75::1]) (using TLSv1 with cipher ADH-CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 7A13A1355; Thu, 5 Dec 2013 15:15:01 +0000 (UTC) Received: from jhbbsd.localnet (unknown [209.249.190.124]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id 03D10B999; Thu, 5 Dec 2013 10:14:58 -0500 (EST) From: John Baldwin To: "=?iso-8859-15?q?Jean-S=E9bastien?= =?iso-8859-15?q?_P=E9dron?=" Subject: Re: svn commit: r258930 - head/sys/dev/drm2 Date: Thu, 5 Dec 2013 10:05:22 -0500 User-Agent: KMail/1.13.5 (FreeBSD/8.4-CBSD-20130906; KDE/4.5.5; amd64; ; ) References: <201312041904.rB4J4vbM043709@svn.freebsd.org> <201312041518.33731.jhb@freebsd.org> <52A04D2E.2040705@FreeBSD.org> In-Reply-To: <52A04D2E.2040705@FreeBSD.org> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-15" Content-Transfer-Encoding: quoted-printable Message-Id: <201312051005.23197.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.7 (bigwig.baldwin.cx); Thu, 05 Dec 2013 10:14:58 -0500 (EST) Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Dec 2013 15:15:01 -0000 On Thursday, December 05, 2013 4:53:50 am Jean-S=E9bastien P=E9dron wrote: > On 04.12.2013 21:18, John Baldwin wrote: > > On Wednesday, December 04, 2013 2:04:57 pm Jean-Sebastien Pedron wrote: > >> Author: dumbbell > >> Date: Wed Dec 4 19:04:56 2013 > >> New Revision: 258930 > >> URL: http://svnweb.freebsd.org/changeset/base/258930 > >> > >> Log: > >> drm: Read PCIER_LINK_CAP/PCIER_LINK_CAP2 from the PCI bridge > >> =20 > >> Before this fix, capabilities were read from vgapci and were incorre= ct. > >=20 > > Eh, vgapci is the right place to read this. The LINK_CAP here is telli= ng > > you the width of the slot you are plugged into, not the width of the ca= rd > > that is plugged into the slot. >=20 > I'm sorry, my knowledge of PCI is very limited (still learning) and I > don't understand your comment. Could you please expand on it? >=20 > I believe this code has the correct result (eg, same result as Linux 3.8 > on the same computer), but maybe I'm doing it wrong and I was just lucky. (First off, I thought you were reading link width, but you're not, you are reading the speed of an individual lane.) Each end of a PCI express link has these config registers. The link capability register contains the maximum supported link speed of that "side" of the link. So the 'pcib' device is the "top" of the link (i.e. the physical slot you plug a card into). When you ask it for its capable link speed, you are getting the maximum speed the slot supports. When you ask vgapci0 for its maximum capable link width, you are getting the maximum speed the card itself supports. So, for example, if you plug a 2.5 GT/s PCI-e card into a 5.0 GT/s slot, the card ('vgapci0') would report= a maximum speed of 2.5, while the slot ('pcibX') would report a maximum speed of 5.0. In addition, each PCI-e device includes a link status register that contains the current active link speed. You can see these register values using 'pciconf -lc'. For example, on my desktop at home, the parent device of vgapci0 (an nvidia card), is pcib1: pcib0 pci0 hostb0 pcib1 pci1 vgapci0 vgapm0 nvidia0 In pciconf I see this output for these devices: pcib1@pci0:0:1:0: class=3D0x060400 card=3D0x77511462 chip=3D0x0101808= 6 rev=3D0x09 hdr=3D0x01 cap 0d[88] =3D PCI Bridge card=3D0x77511462 cap 01[80] =3D powerspec 3 supports D0 D3 current D0 cap 05[90] =3D MSI supports 1 message=20 cap 10[a0] =3D PCI-Express 2 root port slot max data 128(128) link x16(= x16) speed 2.5(5.0) ASPM disabled(L0s/L1) ecap 0002[100] =3D VC 1 max VC0 ecap 0005[140] =3D Root Complex Link Declaration 1 =2E.. vgapci0@pci0:1:0:0: class=3D0x030000 card=3D0x15263842 chip=3D0x104010d= e rev=3D0xa1 hdr=3D0x00 cap 01[60] =3D powerspec 3 supports D0 D3 current D0 cap 05[68] =3D MSI supports 1 message, 64 bit=20 cap 10[78] =3D PCI-Express 2 endpoint max data 128(128) link x16(x16) speed 2.5(2.5) ASPM disabled(L0s/L1) cap 09[b4] =3D vendor (length 20) ecap 0002[100] =3D VC 1 max VC0 ecap 0004[128] =3D Power Budgeting 1 ecap 000b[600] =3D Vendor 1 ID 1 So in this case the "slot" supports a maximum link speed of 5.0 GT/s (it is= a gen3 slot on a SandyBridge motherboard), but the nvidia card is only a gen2 device that supports 2.5GT/s, so the entire link is running at 2.5 GT/s (in the 'speed A(B)' text above, 'B' is the maximum link speed from LINK_CAP and 'A' is the actual link speed from LINK_STA). Can you provide pciconf -lc output from your machine and tell me what you t= hink the function should be returning (i.e. are you trying to determine the speed of the slot, or the speed of the card?) =2D-=20 John Baldwin