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Date:      Thu, 15 Apr 2010 02:44:16 +0000 (UTC)
From:      Juli Mallett <jmallett@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-user@freebsd.org
Subject:   svn commit: r206643 - in user/jmallett/octeon/sys/mips: cavium include mips
Message-ID:  <201004150244.o3F2iGBY062096@svn.freebsd.org>

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Author: jmallett
Date: Thu Apr 15 02:44:16 2010
New Revision: 206643
URL: http://svn.freebsd.org/changeset/base/206643

Log:
  o) Don't duplicate mp_machdep inclusion from the Cavium port.
  o) Fix SMP build.
  o) Clean up tlb.c style some.

Modified:
  user/jmallett/octeon/sys/mips/cavium/files.octeon1
  user/jmallett/octeon/sys/mips/include/tlb.h
  user/jmallett/octeon/sys/mips/mips/machdep.c
  user/jmallett/octeon/sys/mips/mips/mp_machdep.c
  user/jmallett/octeon/sys/mips/mips/tlb.c
  user/jmallett/octeon/sys/mips/mips/trap.c

Modified: user/jmallett/octeon/sys/mips/cavium/files.octeon1
==============================================================================
--- user/jmallett/octeon/sys/mips/cavium/files.octeon1	Thu Apr 15 01:25:17 2010	(r206642)
+++ user/jmallett/octeon/sys/mips/cavium/files.octeon1	Thu Apr 15 02:44:16 2010	(r206643)
@@ -1,7 +1,6 @@
 # $FreeBSD$
 # Octeon Support Files
 #
-mips/mips/mp_machdep.c				optional smp
 mips/cavium/dev/rgmii/octeon_fpa.c		optional rgmii
 mips/cavium/dev/rgmii/octeon_ipd.c 		optional rgmii
 mips/cavium/dev/rgmii/octeon_pko.c		optional rgmii

Modified: user/jmallett/octeon/sys/mips/include/tlb.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/tlb.h	Thu Apr 15 01:25:17 2010	(r206642)
+++ user/jmallett/octeon/sys/mips/include/tlb.h	Thu Apr 15 02:44:16 2010	(r206643)
@@ -29,6 +29,7 @@
 #ifndef	_MACHINE_TLB_H_
 #define	_MACHINE_TLB_H_
 
+void tlb_insert_wired(unsigned, vm_offset_t, pt_entry_t, pt_entry_t);
 void tlb_invalidate_address(struct pmap *, vm_offset_t);
 void tlb_invalidate_all(void);
 void tlb_invalidate_all_user(struct pmap *);

Modified: user/jmallett/octeon/sys/mips/mips/machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/machdep.c	Thu Apr 15 01:25:17 2010	(r206642)
+++ user/jmallett/octeon/sys/mips/mips/machdep.c	Thu Apr 15 02:44:16 2010	(r206643)
@@ -89,6 +89,7 @@ __FBSDID("$FreeBSD$");
 #include <machine/hwfunc.h>
 #include <machine/intr_machdep.h>
 #include <machine/md_var.h>
+#include <machine/tlb.h>
 #ifdef DDB
 #include <sys/kdb.h>
 #include <ddb/ddb.h>
@@ -413,20 +414,17 @@ void
 mips_pcpu_tlb_init(struct pcpu *pcpu)
 {
 	vm_paddr_t pa;
-	struct tlb tlb;
-	int lobits;
+	pt_entry_t pte;
 
 	/*
 	 * Map the pcpu structure at the virtual address 'pcpup'.
 	 * We use a wired tlb index to do this one-time mapping.
 	 */
-	memset(&tlb, 0, sizeof(tlb));
 	pa = vtophys(pcpu);
-	lobits = PG_D | PG_V | PG_G | PG_C_CNC;
-	tlb.tlb_hi = (vm_offset_t)pcpup;
-	tlb.tlb_lo0 = mips_paddr_to_tlbpfn(pa) | lobits;
-	tlb.tlb_lo1 = mips_paddr_to_tlbpfn(pa + PAGE_SIZE) | lobits;
-	Mips_TLBWriteIndexed(PCPU_TLB_ENTRY, &tlb);
+	pte = PG_D | PG_V | PG_G | PG_C_CNC;
+	tlb_insert_wired(PCPU_TLB_ENTRY, (vm_offset_t)pcpup,
+			 TLBLO_PA_TO_PFN(pa) | pte,
+			 TLBLO_PA_TO_PFN(pa + PAGE_SIZE) | pte);
 }
 #endif
 

Modified: user/jmallett/octeon/sys/mips/mips/mp_machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/mp_machdep.c	Thu Apr 15 01:25:17 2010	(r206642)
+++ user/jmallett/octeon/sys/mips/mips/mp_machdep.c	Thu Apr 15 02:44:16 2010	(r206643)
@@ -49,6 +49,7 @@ __FBSDID("$FreeBSD$");
 #include <machine/hwfunc.h>
 #include <machine/intr_machdep.h>
 #include <machine/cache.h>
+#include <machine/tlb.h>
 
 struct pcb stoppcbs[MAXCPU];
 
@@ -295,7 +296,7 @@ smp_init_secondary(u_int32_t cpuid)
 	 */
 	mips_wr_compare(mips_rd_count() + counter_freq / hz);
 
-	enableintr();
+	intr_enable();
 
 	/* enter the scheduler */
 	sched_throw(NULL);

Modified: user/jmallett/octeon/sys/mips/mips/tlb.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/tlb.c	Thu Apr 15 01:25:17 2010	(r206642)
+++ user/jmallett/octeon/sys/mips/mips/tlb.c	Thu Apr 15 02:44:16 2010	(r206643)
@@ -77,6 +77,30 @@ tlb_write_random(void)
 static void tlb_invalidate_one(unsigned);
 
 void
+tlb_insert_wired(unsigned i, vm_offset_t va, pt_entry_t pte0, pt_entry_t pte1)
+{
+	register_t mask, asid;
+	register_t s;
+
+	va &= ~PAGE_MASK;
+
+	s = intr_disable();
+	mask = mips_rd_pagemask();
+	asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
+
+	mips_wr_index(i);
+	mips_wr_pagemask(0);
+	mips_wr_entryhi(TLBHI_ENTRY(va, 0));
+	mips_wr_entrylo0(pte0);
+	mips_wr_entrylo1(pte1);
+	tlb_write_indexed();
+
+	mips_wr_entryhi(asid);
+	mips_wr_pagemask(mask);
+	intr_restore(s);
+}
+
+void
 tlb_invalidate_address(struct pmap *pmap, vm_offset_t va)
 {
 	register_t mask, asid;
@@ -88,12 +112,14 @@ tlb_invalidate_address(struct pmap *pmap
 	s = intr_disable();
 	mask = mips_rd_pagemask();
 	asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
+
 	mips_wr_pagemask(0);
 	mips_wr_entryhi(TLBHI_ENTRY(va, pmap_asid(pmap)));
 	tlb_probe();
 	i = mips_rd_index();
 	if (i >= 0)
 		tlb_invalidate_one(i);
+
 	mips_wr_entryhi(asid);
 	mips_wr_pagemask(mask);
 	intr_restore(s);
@@ -109,8 +135,10 @@ tlb_invalidate_all(void)
 	s = intr_disable();
 	mask = mips_rd_pagemask();
 	asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
+
 	for (i = mips_rd_wired(); i < num_tlbentries; i++)
 		tlb_invalidate_one(i);
+
 	mips_wr_entryhi(asid);
 	mips_wr_pagemask(mask);
 	intr_restore(s);
@@ -126,6 +154,7 @@ tlb_invalidate_all_user(struct pmap *pma
 	s = intr_disable();
 	mask = mips_rd_pagemask();
 	asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
+
 	for (i = mips_rd_wired(); i < num_tlbentries; i++) {
 		register_t uasid;
 
@@ -148,6 +177,7 @@ tlb_invalidate_all_user(struct pmap *pma
 		}
 		tlb_invalidate_one(i);
 	}
+
 	mips_wr_entryhi(asid);
 	mips_wr_pagemask(mask);
 	intr_restore(s);
@@ -166,6 +196,7 @@ tlb_update(struct pmap *pmap, vm_offset_
 	s = intr_disable();
 	mask = mips_rd_pagemask();
 	asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
+
 	mips_wr_pagemask(0);
 	mips_wr_entryhi(TLBHI_ENTRY(va, pmap_asid(pmap)));
 	tlb_probe();
@@ -180,6 +211,7 @@ tlb_update(struct pmap *pmap, vm_offset_
 		}
 		tlb_write_indexed();
 	}
+
 	mips_wr_entryhi(asid);
 	mips_wr_pagemask(mask);
 	intr_restore(s);

Modified: user/jmallett/octeon/sys/mips/mips/trap.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/trap.c	Thu Apr 15 01:25:17 2010	(r206642)
+++ user/jmallett/octeon/sys/mips/mips/trap.c	Thu Apr 15 02:44:16 2010	(r206643)
@@ -419,7 +419,7 @@ trap(struct trapframe *trapframe)
 #ifdef SMP
 			/* It is possible that some other CPU changed m-bit */
 			if (!pte_test(pte, PG_V) || pte_test(pte, PG_D)) {
-				pmap_update_page(pmap, trapframe->badvaddr, entry);
+				pmap_update_page(pmap, trapframe->badvaddr, *pte);
 				PMAP_UNLOCK(pmap);
 				goto out;
 			}
@@ -920,8 +920,8 @@ dofault:
 #if !defined(SMP) && (defined(DDB) || defined(DEBUG))
 		trapDump("fpintr");
 #else
-		printf("FPU Trap: PC %x CR %x SR %x\n",
-		    trapframe->pc, trapframe->cause, trapframe->sr);
+		printf("FPU Trap: PC %#jx CR %x SR %x\n",
+		    (intmax_t)trapframe->pc, (unsigned)trapframe->cause, (unsigned)trapframe->sr);
 		goto err;
 #endif
 



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