Date: Sat, 15 Jun 1996 20:44:18 -0700 From: "Michael L. VanLoon -- HeadCandy.com" <michaelv@HeadCandy.com> To: port-i386@netbsd.org, hackers@freebsd.org, hardware@freebsd.org Subject: write-through bit for 486's with write-back cache Message-ID: <199606160344.UAA14100@MindBender.HeadCandy.com>
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I can't find this anywhere on AMD's or Intel's web sites. Their
programming docs are pathetically lacking in the web access category.
On the AMD "enhanced" 486DX4 and 5x86 chips, they have write-back
on-chip cache. However, they mention a bit in CR0 called "PWT" that
supposedly makes all cache lines always marked "shared", which
effectively makes the cache write-through.
Does anyone have a technical reference or programmer's manual for
either the AMD 486DX4, 5x86, or Intel 486DX4 chips that specifically
details CR0 and this "PWT" bit? I'm assuming the Intel 486DX4
"writeback-enhanced" chips use the same CR0 bit. Hopefully I am
assuming correctly.
Alternatively, does anyone have a Pentium programmer's manual they
could look in to see if they Pentium has this PWT bit in it's CR0
register.
Thanks for your help...
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Michael L. VanLoon michaelv@HeadCandy.com
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