From owner-freebsd-arch@FreeBSD.ORG Sat Apr 11 18:29:14 2009 Return-Path: Delivered-To: arch@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 5506F1065670; Sat, 11 Apr 2009 18:29:14 +0000 (UTC) (envelope-from nwhitehorn@freebsd.org) Received: from argol.doit.wisc.edu (argol.doit.wisc.edu [144.92.197.212]) by mx1.freebsd.org (Postfix) with ESMTP id 286ED8FC1D; Sat, 11 Apr 2009 18:29:13 +0000 (UTC) (envelope-from nwhitehorn@freebsd.org) MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: text/plain; charset=ISO-8859-1; format=flowed Received: from avs-daemon.smtpauth3.wiscmail.wisc.edu by smtpauth3.wiscmail.wisc.edu (Sun Java(tm) System Messaging Server 7.0-5.01 32bit (built Feb 19 2009)) id <0KHY007005W9GS00@smtpauth3.wiscmail.wisc.edu>; Sat, 11 Apr 2009 12:28:57 -0500 (CDT) Received: from comporellon.tachypleus.net ([unknown] [76.201.152.222]) by smtpauth3.wiscmail.wisc.edu (Sun Java(tm) System Messaging Server 7.0-5.01 32bit (built Feb 19 2009)) with ESMTPSA id <0KHY002ZY5W37Q50@smtpauth3.wiscmail.wisc.edu>; Sat, 11 Apr 2009 12:28:56 -0500 (CDT) Date: Sat, 11 Apr 2009 12:28:51 -0500 From: Nathan Whitehorn In-reply-to: To: Robert Watson Message-id: <49E0D353.7090308@freebsd.org> X-Spam-Report: AuthenticatedSender=yes, SenderIP=76.201.152.222 X-Spam-PmxInfo: Server=avs-10, Version=5.5.1.360522, Antispam-Engine: 2.6.1.350677, Antispam-Data: 2009.4.11.171624, SenderIP=76.201.152.222 References: User-Agent: Thunderbird 2.0.0.21 (X11/20090405) Cc: arch@FreeBSD.org Subject: Re: Simple #define for cache line size X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 11 Apr 2009 18:29:14 -0000 Robert Watson wrote: > > > NetBSD, FYI, defines CACHE_LINE_SIZE as a global constant in param.h, > but I'm going with an MD definition as I suspect people will want to > do different things on different architectures (and there is > variation). I've defaulted all architectures to 64 bytes, but I > suspect a number would prefer to use 32. For what it's worth, this is per-CPU variable on PowerPC and detected at runtime. Most of the CPUs we support have 32 byte cache lines, but some (e.g. the G5) use 128 bytes. I'm not sure there is a general solution in this case, but that's the situation on PPC. -Nathan