Date: Thu, 02 Jan 1997 11:21:03 -0700 From: Warner Losh <imp@village.org> To: Michael Smith <msmith@atrad.adelaide.edu.au> Cc: hmmm@alaska.net, hackers@freebsd.org Subject: Re: Ints Message-ID: <E0vfrlH-0003ne-00@rover.village.org> In-Reply-To: Your message of "Thu, 02 Jan 1997 22:04:02 %2B1030." <199701021134.WAA16141@genesis.atrad.adelaide.edu.au> References: <199701021134.WAA16141@genesis.atrad.adelaide.edu.au>
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In message <199701021134.WAA16141@genesis.atrad.adelaide.edu.au> Michael Smith writes: : You're wrong. There is no automatic interrupt-acknowledge on the ISA : bus. The PIC interrupts the processor when an input goes from : inactive to active. It is the processor's responsibility to : manipulate the peripheral so that the input goes inactive again. If : it fails to do so, there will be no more interrupts from it. Finito. In fact, on the MIPS based PCs that were shipped a few years ago, the OS had to deal with almost all of the PIC stuff by hand. The PIC processor wasn't quite powerful enough to do chaining (or wasn't configured to do it), etc. The ISA bus is a horrible abortion wrt other hardware that is available. All the reasonable things one can assume about harware is broken by the ISA bus. Sun had a lot of growning pains when they ported Solaris to x86 because they felt that no sane person would ever design hardware like the ISA bus. Needless to say, they had to fix a bunch of assumptions in their kernels and APIs to allow for things to work reasonably well on the Intel/ISA architecture. It is very un-sun-like (eg not sbus or VME at all). The good news is that they seem to have it fixed and things work on the intel at least as well as they work on Sparc. Warner
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