Date: Tue, 12 Jun 2018 16:47:33 +0000 (UTC) From: Ruslan Bukin <br@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r335005 - head/sys/riscv/riscv Message-ID: <201806121647.w5CGlX9j099475@repo.freebsd.org>
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Author: br Date: Tue Jun 12 16:47:33 2018 New Revision: 335005 URL: https://svnweb.freebsd.org/changeset/base/335005 Log: Release secondary cores from WFI (wait for interrupt) by sending them an IPI. This does not work however yet in QEMU. As a temporary workaround set software interrupt pending bit manually on a local core to ensure WFI doesn't halt the hart. This is required to smpboot in QEMU. Sponsored by: DARPA, AFRL Modified: head/sys/riscv/riscv/mp_machdep.c Modified: head/sys/riscv/riscv/mp_machdep.c ============================================================================== --- head/sys/riscv/riscv/mp_machdep.c Tue Jun 12 16:45:52 2018 (r335004) +++ head/sys/riscv/riscv/mp_machdep.c Tue Jun 12 16:47:33 2018 (r335005) @@ -181,6 +181,7 @@ riscv64_cpu_attach(device_t dev) static void release_aps(void *dummy __unused) { + uintptr_t mask; int cpu, i; if (mp_ncpus == 1) @@ -191,6 +192,14 @@ release_aps(void *dummy __unused) atomic_store_rel_int(&aps_ready, 1); + /* Wake up the other CPUs */ + mask = 0; + + for (i = 1; i < mp_ncpus; i++) + mask |= (1 << i); + + sbi_send_ipi(&mask); + printf("Release APs\n"); for (i = 0; i < 2000; i++) { @@ -216,6 +225,11 @@ init_secondary(uint64_t cpu) /* Setup the pcpu pointer */ pcpup = &__pcpu[cpu]; __asm __volatile("mv gp, %0" :: "r"(pcpup)); + + /* Workaround: make sure wfi doesn't halt the hart */ + intr_disable(); + csr_set(sie, SIE_SSIE); + csr_set(sip, SIE_SSIE); /* Spin until the BSP releases the APs */ while (!aps_ready)
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