Date: Sat, 18 Mar 1995 14:06:04 -0800 (PST) From: "Rodney W. Grimes" <rgrimes@gndrsh.aac.dev.com> To: dufault@hda.com (Peter Dufault) Cc: hackers@freefall.cdrom.com Subject: Re: SMP work Message-ID: <199503182206.OAA22038@gndrsh.aac.dev.com> In-Reply-To: <199503181958.OAA02775@hda.com> from "Peter Dufault" at Mar 18, 95 02:58:34 pm
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> > Rodney W. Grimes writes: > > > > [CC: trimmed] > > ... > > > Which brings up the interesting question of whether or not we ever > > > intend to get serious about this port. Jack is clearly out of the > > > picture here, both for this and very possibly the SMP stuff, and I > > > think it's time to either put it firmly aside for the foreseeable > > > future or reassign one or both of these projects elsewhere. > > > > If Jack is out of the picture on SMP I can start the basics of it > > rolling. I have been putting off on getting the dual PCI/ISA version > > of the ASUS board for a week now to try and help Jack with getting > > some code he is having problems with up and running. I already own > > the CPU chips, so this is not that large of a cash outlay for me. > > I'd like to see a proposal for the kernel locking model. After many > years of multithreaded programming and three years of Alliant MP work > I'm always thinking about locking data structures to lock out the > other CPUs. If we had a working model we could start to add some of > this stuff when adding new code. Jack talked to me breifly on this topic, but he was really asking me to help him with the low level idosyncrcious of how the x86 family starts up and how the APIC (Advanced Priority Interrupt Controller) works. I think that the locking model to be used should be discussed amongst us, as there are several alternatives. I have no firm opinions on this issue. > > > I know Jack put quite an effort into just getting the second CPU to > > start up and from my last communications with him he had still not > > got it to switch into protected mode. > > What is the I/O model for this ASUS? Do they have separate I/O > busses, a single bus, or what? It wouldn't be SMP if they had separate buses now would it :-). The ISA/EISA/PCI buses and cache and memory are shared by 2 CPU chips. An Intel P54C CPU chip (that is what all the implementations I have seen of Intel MP Spec are using) have a built in APIC (yes, your 90 and 100Mhz Pentiums have an APIC in them, the single CPU motherboards disable it with one of the pins as best I can tell). These APIC's can be used for sending Interter Processor Interrupts, that is how you start the second CPU up. They also allow you to control which CPU gets which interrupts. You can prefer certain interrupts to certain CPU's or you can have it dispatch the interrupt to the lowest priority CPU, etc etc.. Since the APIC is built into the CPU the you don't have the high I/O latency of talking to things like 8259's to control them. There is a paper on the Intel MP spec on ftp.intel.com. The file name is mpspec.ps, but I forget what directory it is in. > I assume the MP architecture is an > Intel standard with Intel support chips that I know little about. Yes. > (Intel licenced Alliant's Concurrency Control Unit for future > generations of the i860 - yeah, right. Are they continuing that > with their "merchant" MP?) I have no idea what they did with the i860 and Alliants stuff, so I can not say if they are continuing that. Somehow I doubt it very much since the iX60 group is over in the SuperComputer division, which is more like a seperate company. -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Custom computers for FreeBSD
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