Date: Tue, 7 Jun 2016 18:50:36 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r301561 - in head/sys/arm: arm include Message-ID: <201606071850.u57Ioa1b004408@repo.freebsd.org>
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Author: andrew Date: Tue Jun 7 18:50:36 2016 New Revision: 301561 URL: https://svnweb.freebsd.org/changeset/base/301561 Log: Start to clean MIDR values using the CPUID scheme. We don't need to know the exact CPU we are running on to set the cpu functions. Relax the check to ignore the CPU revision. Even so this may still be too specific. Reviewed by: mmel Sponsored by: ABT Systems Ltd Differential Revision: https://reviews.freebsd.org/D6504 Modified: head/sys/arm/arm/cpufunc.c head/sys/arm/include/armreg.h Modified: head/sys/arm/arm/cpufunc.c ============================================================================== --- head/sys/arm/arm/cpufunc.c Tue Jun 7 18:23:22 2016 (r301560) +++ head/sys/arm/arm/cpufunc.c Tue Jun 7 18:50:36 2016 (r301561) @@ -761,25 +761,19 @@ set_cpufuncs() } #endif /* CPU_ARM1176 */ #if defined(CPU_CORTEXA) || defined(CPU_KRAIT) - if (cputype == CPU_ID_CORTEXA5 || - cputype == CPU_ID_CORTEXA7 || - cputype == CPU_ID_CORTEXA8R1 || - cputype == CPU_ID_CORTEXA8R2 || - cputype == CPU_ID_CORTEXA8R3 || - cputype == CPU_ID_CORTEXA9R1 || - cputype == CPU_ID_CORTEXA9R2 || - cputype == CPU_ID_CORTEXA9R3 || - cputype == CPU_ID_CORTEXA9R4 || - cputype == CPU_ID_CORTEXA12R0 || - cputype == CPU_ID_CORTEXA15R0 || - cputype == CPU_ID_CORTEXA15R1 || - cputype == CPU_ID_CORTEXA15R2 || - cputype == CPU_ID_CORTEXA15R3 || - cputype == CPU_ID_KRAIT300R0 || - cputype == CPU_ID_KRAIT300R1 ) { + switch(cputype & CPU_ID_SCHEME_MASK) { + case CPU_ID_CORTEXA5: + case CPU_ID_CORTEXA7: + case CPU_ID_CORTEXA8: + case CPU_ID_CORTEXA9: + case CPU_ID_CORTEXA12: + case CPU_ID_CORTEXA15: + case CPU_ID_KRAIT300: cpufuncs = cortexa_cpufuncs; get_cachetype_cp15(); goto out; + default: + break; } #endif /* CPU_CORTEXA */ Modified: head/sys/arm/include/armreg.h ============================================================================== --- head/sys/arm/include/armreg.h Tue Jun 7 18:23:22 2016 (r301560) +++ head/sys/arm/include/armreg.h Tue Jun 7 18:50:36 2016 (r301561) @@ -72,10 +72,16 @@ #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ #define CPU_ID_DEC 0x44000000 /* 'D' */ -#define CPU_ID_INTEL 0x69000000 /* 'i' */ +#define CPU_ID_MOTOROLA 0x4D000000 /* 'M' */ +#define CPU_ID_QUALCOM 0x51000000 /* 'Q' */ #define CPU_ID_TI 0x54000000 /* 'T' */ +#define CPU_ID_MARVELL 0x56000000 /* 'V' */ +#define CPU_ID_INTEL 0x69000000 /* 'i' */ #define CPU_ID_FARADAY 0x66000000 /* 'f' */ +#define CPU_ID_VARIANT_SHIFT 20 +#define CPU_ID_VARIANT_MASK 0x00f00000 + /* How to decide what format the CPUID is in. */ #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) @@ -92,7 +98,6 @@ #define CPU_ID_ARCH_V5TEJ 0x00060000 #define CPU_ID_ARCH_V6 0x00070000 #define CPU_ID_CPUID_SCHEME 0x000f0000 -#define CPU_ID_VARIANT_MASK 0x00f00000 /* Next three nybbles are part number */ #define CPU_ID_PARTNO_MASK 0x0000fff0 @@ -123,22 +128,35 @@ #define CPU_ID_ARM1136JS 0x4107b360 #define CPU_ID_ARM1136JSR1 0x4117b360 #define CPU_ID_ARM1176JZS 0x410fb760 -#define CPU_ID_CORTEXA5 0x410fc050 -#define CPU_ID_CORTEXA7 0x410fc070 -#define CPU_ID_CORTEXA8R1 0x411fc080 -#define CPU_ID_CORTEXA8R2 0x412fc080 -#define CPU_ID_CORTEXA8R3 0x413fc080 -#define CPU_ID_CORTEXA9R1 0x411fc090 -#define CPU_ID_CORTEXA9R2 0x412fc090 -#define CPU_ID_CORTEXA9R3 0x413fc090 -#define CPU_ID_CORTEXA9R4 0x414fc090 -#define CPU_ID_CORTEXA12R0 0x410fc0d0 -#define CPU_ID_CORTEXA15R0 0x410fc0f0 -#define CPU_ID_CORTEXA15R1 0x411fc0f0 -#define CPU_ID_CORTEXA15R2 0x412fc0f0 -#define CPU_ID_CORTEXA15R3 0x413fc0f0 -#define CPU_ID_KRAIT300R0 0x510f06f0 /* Snapdragon S4 Pro/APQ8064 */ -#define CPU_ID_KRAIT300R1 0x511f06f0 + +/* CPUs that follow the CPUID scheme */ +#define CPU_ID_SCHEME_MASK \ + (CPU_ID_IMPLEMENTOR_MASK | CPU_ID_ARCH_MASK | CPU_ID_PARTNO_MASK) + +#define CPU_ID_CORTEXA5 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc050) +#define CPU_ID_CORTEXA7 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc070) +#define CPU_ID_CORTEXA8 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc080) +#define CPU_ID_CORTEXA8R1 (CPU_ID_CORTEXA8 | (1 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA8R2 (CPU_ID_CORTEXA8 | (2 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA8R3 (CPU_ID_CORTEXA8 | (3 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA9 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc090) +#define CPU_ID_CORTEXA9R1 (CPU_ID_CORTEXA9 | (1 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA9R2 (CPU_ID_CORTEXA9 | (2 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA9R3 (CPU_ID_CORTEXA9 | (3 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA9R4 (CPU_ID_CORTEXA9 | (4 << CPU_ID_VARIANT_SHIFT)) +/* XXX: Cortx-A12 is the old name for this part, it has been renamed the A17 */ +#define CPU_ID_CORTEXA12 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc0d0) +#define CPU_ID_CORTEXA12R0 (CPU_ID_CORTEXA12 | (0 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA15 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc0f0) +#define CPU_ID_CORTEXA15R0 (CPU_ID_CORTEXA15 | (0 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA15R1 (CPU_ID_CORTEXA15 | (1 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA15R2 (CPU_ID_CORTEXA15 | (2 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_CORTEXA15R3 (CPU_ID_CORTEXA15 | (3 << CPU_ID_VARIANT_SHIFT)) + +#define CPU_ID_KRAIT300 (CPU_ID_QUALCOM | CPU_ID_CPUID_SCHEME | 0x06f0) +/* Snapdragon S4 Pro/APQ8064 */ +#define CPU_ID_KRAIT300R0 (CPU_ID_KRAIT300 | (0 << CPU_ID_VARIANT_SHIFT)) +#define CPU_ID_KRAIT300R1 (CPU_ID_KRAIT300 | (1 << CPU_ID_VARIANT_SHIFT)) #define CPU_ID_TI925T 0x54029250 #define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */
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