Date: Wed, 09 Feb 2011 11:34:21 -0600 From: Mark Tinguely <marktinguely@gmail.com> To: Marcel Moolenaar <xcllnt@mac.com> Cc: arm@freebsd.org Subject: Re: Elimination of cpu_l2cache_* functions Message-ID: <4D52D01D.7060204@gmail.com> In-Reply-To: <CFDFD654-F62D-4BA8-83F8-95AC0A38437F@mac.com> References: <857AA8D9-5C41-4D80-A3B5-0D29BE051014@mac.com> <20110209095630.GA57320@ci0.org> <CFDFD654-F62D-4BA8-83F8-95AC0A38437F@mac.com>
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On 2/9/2011 10:25 AM, Marcel Moolenaar wrote: > On Feb 9, 2011, at 1:56 AM, Olivier Houchard wrote: > >> Hi Marcel, >> >> On Mon, Feb 07, 2011 at 10:43:54AM -0800, Marcel Moolenaar wrote: >>> All, >>> >>> I've been reviewing the use of the cpu_l2cache_* functions and found >>> that 1) they're missing from cpu_witch() and 2) they are always used >>> in conjunction with either cpu_idcache_* or cpu_dcache_*. >>> >>> Since most CPU variants define them as null ops, isn't it better to >>> incorporate the functionality of cpu_l2cache_* in cpu_idcache_* and >>> cpu_dcache_* and eliminate them altogether? >>> >>> Any objections to me removing cpu_l2cache_* and therefore changing >>> the semantics of cpu_idcache_* and cpu_dcahce_* to apply to all >>> relevant cache levels? > Hi Olivier, good to hear from you, > >> I chose to make the l2cache functions separate from the [i]dcache functions >> because there's a number of cases where L1 cache flush was needed, but not L2, >> and that would be a performance penalty to do both. > I'll take it from this that the L2 is PIPT for the Xscale core 3 > as well, right? > >> Also, more CPU variants define them as null ops now, but most new arm cpus >> come with a L2 cache,, so we need to think about it carefully. > Agreed. If the L2 cache is PIPT, then we should not do tie L1& L2 > together and I'd like to change the code to remove the L2 cache > operations from most places where we have them now. My point is the L2 caches better be PIPT. If the L2 cache are virtual indexed and we do not flush them on context change, then we could have multiple copies in the L2 cache when we share a page and the width of the level 2 cache is larger than a page. It only make sense from the hardware design side to make the L2 cache PIPT. > What I'm thinking about is the following: introduce pmap_switch(), > as we have it on ia64. This function is called from cpu_switch to > replace the existing active pmap with a new one. In pmap_switch() > we flush the VIVT caches *IFF* the new pmap is different from the > old (=currently active) pmap. Consequently, we're not going to > flush the VIVT caches when we switch between kernel threads, nor > do we flush the caches when we switch between threads in the > same process. In all other cases we'll flush the VIVT caches. > > pmap_switch() is also called when a pmap interface function gets > a pmap to work on. The interface function switches the pmap, (if > applicable) which may or may not force a VIVT cache operation. > The pmap interface function does it's work, after which it switches > back to the pmap that was active on entry to the function. This > then could also trigger VIVT cache operations. > > In any case: I'm thinking that this removes most of the explicit > calls to the cache functions while still guaranteing coherency. > > I need to look into the aliasing case to see how that is handled. > I have some ideas for that too... > > Thoughts? > There are places we can remove redundant cache operations; pmap_qenter() comes to mind. A lot of the cache operations outside of a context switch occur because we share a page within the same memory map (I think that is what you mean by the aliasing case), we turn access or writing off, and for dma. For VIVT caches, I can't see these operations going away. The page copying and zeroing are other examples and it seems like they need cache operations. --Mark.
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