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Date:      Sun, 13 Aug 2006 16:17:42 +1000
From:      Andrew Reilly <andrew@areilly.bpc-users.org>
To:        obrien@freebsd.org
Cc:        freebsd-amd64@freebsd.org
Subject:   Re: NVE Timeout
Message-ID:  <20060813161742.3a8cdf54@duncan.reilly.home>
In-Reply-To: <20060813010321.GC47774@dragon.NUXI.org>
References:  <..1153169042.squirrel@risei.net> <Pine.GSO.4.62.0607171545330.20439@harper.uchicago.edu> <44BC8B44.8010900@uni-mainz.de> <20060813010321.GC47774@dragon.NUXI.org>

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On Sat, 12 Aug 2006 18:03:21 -0700
"David O'Brien" <obrien@freebsd.org> wrote:

> On Tue, Jul 18, 2006 at 09:18:28AM +0200, O. Hartmann wrote:
> > Is there any expected date when nfe will find its way into 6.X?
> 
> Working to make it in 6.2-RELEASE.  I don't know that it will be the
> default driver for nVidia NIC's - I haven't decided wheather to leave
> nve(4) as the default driver or not.

More importantly (for me): will that include the ciphy patch that
was associated with the nfe driver?  (attached)  That's the bit
that I have to keep applying every time I track STABLE.  The
driver itself seems fairly stable and independent of minor kernel
revisions. (And works great, for me.)

Cheers,

-- 
Andrew

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--- ciphy.c.orig	Thu Jan  6 10:42:55 2005
+++ ciphy.c	Sun Apr 30 00:15:58 2006
@@ -386,6 +386,12 @@
 	status = PHY_READ(sc, CIPHY_MII_AUXCSR);
 	speed = status & CIPHY_AUXCSR_SPEED;
 
+	if (strcmp(device_get_name(device_get_parent(sc->mii_dev)), "nfe") == 0) {
+		/* need to set for 2.5V RGMII for NVIDIA adapters */
+		PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_INTSEL_RGMII);
+		PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_IOVOL_2500MV);
+	}
+
 	switch (model) {
 	case MII_MODEL_CICADA_CS8201:
 
--- ciphyreg.h.orig	Thu Jan  6 10:42:55 2005
+++ ciphyreg.h	Sat Apr 29 23:36:27 2006
@@ -251,6 +251,16 @@
 /* Extended PHY control register #1 */
 #define CIPHY_MII_ECTL1		0x17
 #define CIPHY_ECTL1_ACTIPHY	0x0020	/* Enable ActiPHY power saving */
+#define CIPHY_ECTL1_IOVOL	0x0e00	/* MAC interface and I/O voltage select */
+#define CIPHY_ECTL1_INTSEL	0xf000	/* select MAC interface */
+
+#define CIPHY_IOVOL_3300MV	0x0000	/* 3.3V for I/O pins */
+#define CIPHY_IOVOL_2500MV	0x0200	/* 2.5V for I/O pins */
+
+#define CIPHY_INTSEL_GMII	0x0000	/* GMII/MII */
+#define CIPHY_INTSEL_RGMII	0x1000
+#define CIPHY_INTSEL_TBI	0x2000
+#define CIPHY_INTSEL_RTBI	0x3000
 
 /* Extended PHY control register #2 */
 #define CIPHY_MII_ECTL2		0x18

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