Date: Wed, 24 Oct 2012 14:27:31 -0700 From: Adrian Chadd <adrian@freebsd.org> To: Jim Harris <jimharris@freebsd.org> Cc: freebsd-arch@freebsd.org Subject: Re: CACHE_LINE_SIZE on x86 Message-ID: <CAJ-VmonzxfKy7QtHK86nUQRYs2ULuMt20m6E4B3FtNhYByorMA@mail.gmail.com> In-Reply-To: <CAJP=Hc_F%2B-RdD=XZ7ikBKVKE_XW88Y35Xw0bYE6gGURLPDOAWw@mail.gmail.com> References: <CAJP=Hc_F%2B-RdD=XZ7ikBKVKE_XW88Y35Xw0bYE6gGURLPDOAWw@mail.gmail.com>
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On 24 October 2012 12:13, Jim Harris <jimharris@freebsd.org> wrote: > While investigating padding of the ULE scheduler locks (r242014), I > recently discovered that CACHE_LINE_SIZE on x86 is defined as 128 (not > 64). From what I can tell from svn logs, this was to account for 128 > byte cache "sectors" that existed on the NetBurst micro architecture > CPUs. > > I'm curious if there's been consideration in changing this back to 64? > With maybe a kernel config option to modify it? On 2S systems (but > not on 1S systems), I see a benefit using CACHE_LINE_SIZE=128 for the > scheduler locks. I suspect this is related to data prefetching but am > still running experiments to verify. Well, is it worth maintaining multiple alignment options, for aligning different things? eg cache alignment for memory allocations, larger alignment for compile-time structure alignment, etc? Adrian
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