From owner-svn-src-user@FreeBSD.ORG Fri Mar 5 02:52:24 2010 Return-Path: Delivered-To: svn-src-user@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id E9DD2106564A; Fri, 5 Mar 2010 02:52:23 +0000 (UTC) (envelope-from jmallett@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id D84FD8FC16; Fri, 5 Mar 2010 02:52:23 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o252qNxe066635; Fri, 5 Mar 2010 02:52:23 GMT (envelope-from jmallett@svn.freebsd.org) Received: (from jmallett@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o252qNLM066598; Fri, 5 Mar 2010 02:52:23 GMT (envelope-from jmallett@svn.freebsd.org) Message-Id: <201003050252.o252qNLM066598@svn.freebsd.org> From: Juli Mallett Date: Fri, 5 Mar 2010 02:52:23 +0000 (UTC) To: src-committers@freebsd.org, svn-src-user@freebsd.org X-SVN-Group: user MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r204747 - in user/jmallett/octeon/sys: conf mips/cavium mips/conf mips/include mips/mips X-BeenThere: svn-src-user@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the experimental " user" src tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Mar 2010 02:52:24 -0000 Author: jmallett Date: Fri Mar 5 02:52:23 2010 New Revision: 204747 URL: http://svn.freebsd.org/changeset/base/204747 Log: Make o32 work on my branch again. Most importantly: o) Refactor octeon_pcmap_regs.h to reduce the number of functions written for each ABI/ISA, and use macros to write the trivial ones for different types. Added: user/jmallett/octeon/sys/mips/conf/OCTEON1-o32 Modified: user/jmallett/octeon/sys/conf/Makefile.mips user/jmallett/octeon/sys/conf/ldscript.mips.octeon1.32 user/jmallett/octeon/sys/mips/cavium/octeon_pcmap_regs.h user/jmallett/octeon/sys/mips/include/_bus.h user/jmallett/octeon/sys/mips/mips/bus_space_generic.c Modified: user/jmallett/octeon/sys/conf/Makefile.mips ============================================================================== --- user/jmallett/octeon/sys/conf/Makefile.mips Fri Mar 5 00:54:28 2010 (r204746) +++ user/jmallett/octeon/sys/conf/Makefile.mips Fri Mar 5 02:52:23 2010 (r204747) @@ -61,6 +61,9 @@ HACK_EXTRA_FLAGS+=-Wl,-m,elf64btsmip_fbs .if defined(TARGET_N32) SYSTEM_LD+=-m elf32btsmipn32_fbsd HACK_EXTRA_FLAGS+=-Wl,-m,elf32btsmipn32_fbsd +.else +SYSTEM_LD+=-m elf32btsmip_fbsd +HACK_EXTRA_FLAGS+=-Wl,-m,elf32btsmip_fbsd .endif .else CFLAGS+=-EL @@ -75,6 +78,9 @@ HACK_EXTRA_FLAGS+=-Wl,-m,elf64ltsmip_fbs .if defined(TARGET_N32) SYSTEM_LD+=-m elf32ltsmipn32_fbsd HACK_EXTRA_FLAGS+=-Wl,-m,elf32ltsmipn32_fbsd +.else +SYSTEM_LD+=-m elf32ltsmip_fbsd +HACK_EXTRA_FLAGS+=-Wl,-m,elf32ltsmip_fbsd .endif .endif Modified: user/jmallett/octeon/sys/conf/ldscript.mips.octeon1.32 ============================================================================== --- user/jmallett/octeon/sys/conf/ldscript.mips.octeon1.32 Fri Mar 5 00:54:28 2010 (r204746) +++ user/jmallett/octeon/sys/conf/ldscript.mips.octeon1.32 Fri Mar 5 02:52:23 2010 (r204747) @@ -1,13 +1,13 @@ -/* - * This product includes software developed by the University of - * California, Berkeley and its contributors." -*/ +TARGET(elf32-tradbigmips) OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) + __DYNAMIC = 0; +PROVIDE (_DYNAMIC = 0); SECTIONS { . = KERNLOADADDR + SIZEOF_HEADERS; + .text . : { *(.text) *(.dynamic) Modified: user/jmallett/octeon/sys/mips/cavium/octeon_pcmap_regs.h ============================================================================== --- user/jmallett/octeon/sys/mips/cavium/octeon_pcmap_regs.h Fri Mar 5 00:54:28 2010 (r204746) +++ user/jmallett/octeon/sys/mips/cavium/octeon_pcmap_regs.h Fri Mar 5 02:52:23 2010 (r204747) @@ -91,74 +91,65 @@ extern struct pcpu *cpuid_to_pcpu[]; #define OCTEON_SYNCWS __asm __volatile (".word 0x14f" : : ) #if defined(__mips_n64) +#define oct_write64(a, v) (*(volatile uint64_t *)(a) = (uint64_t)(v)) +#define oct_write8_x8(a, v) (*(volatile uint8_t *)(a) = (uint8_t)(v)) -static inline void oct_write64 (uint64_t csr_addr, uint64_t val64) -{ - volatile uint64_t *ptr = (volatile uint64_t *) csr_addr; - *ptr = val64; -} +#define OCT_READ(n, t) \ +static inline t oct_read ## n(uintptr_t a) \ +{ \ + volatile t *p = (volatile t *)a; \ + return (*p); \ +} + +OCT_READ(8, uint8_t); +OCT_READ(16, uint16_t); +OCT_READ(32, uint32_t); +OCT_READ(64, uint64_t); -static inline void oct_write64_int64 (uint64_t csr_addr, int64_t val64i) +#elif defined(__mips_n32) || defined(__mips_o32) +#if defined(__mips_n32) +static inline void oct_write64 (uint64_t csr_addr, uint64_t val64) { - volatile int64_t *ptr = (volatile int64_t *) csr_addr; - *ptr = val64i; + __asm __volatile ( + ".set push\n" + ".set mips64\n" + "sd %0, 0(%1)\n" + ".set pop\n" + : + : "r"(val64), "r"(csr_addr)); } static inline void oct_write8_x8 (uint64_t csr_addr, uint8_t val8) { - volatile uint64_t *ptr = (volatile uint64_t *) csr_addr; - *ptr = (uint64_t) val8; -} - -static inline void oct_write8 (uint64_t csr_addr, uint8_t val8) -{ - oct_write64(csr_addr, (uint64_t) val8); -} - -static inline void oct_write16 (uint64_t csr_addr, uint16_t val16) -{ - oct_write64(csr_addr, (uint64_t) val16); -} - -static inline void oct_write32 (uint64_t csr_addr, uint32_t val32) -{ - oct_write64(csr_addr, (uint64_t) val32); -} - -static inline uint8_t oct_read8 (uint64_t csr_addr) -{ - volatile uint8_t *ptr = (volatile uint8_t *) csr_addr; - return (*ptr); -} - -static inline uint16_t oct_read16 (uint64_t csr_addr) -{ - volatile uint16_t *ptr = (volatile uint16_t *) csr_addr; - return (*ptr); -} - - -static inline uint32_t oct_read32 (uint64_t csr_addr) -{ - volatile uint32_t *ptr = (volatile uint32_t *) csr_addr; - return (*ptr); -} - -static inline uint64_t oct_read64 (uint64_t csr_addr) -{ - volatile uint64_t *ptr = (volatile uint64_t *) csr_addr; - return (*ptr); -} - -static inline int32_t oct_readint32 (uint64_t csr_addr) -{ - volatile int32_t *ptr = (volatile int32_t *) csr_addr; - return (*ptr); + __asm __volatile ( + ".set push\n" + ".set mips64\n" + "sb %0, 0(%1)\n" + ".set pop\n" + : + : "r"(val8), "r"(csr_addr)); } - - -#elif defined(__mips_n32) +#define OCT_READ(n, t, insn) \ +static inline t oct_read ## n(uint64_t a) \ +{ \ + uint64_t tmp; \ + \ + __asm __volatile ( \ + ".set push\n" \ + ".set mips64\n" \ + insn "\t%0, 0(%1)\n" \ + ".set pop\n" \ + : "=r"(tmp) \ + : "r"(a)); \ + return ((t)tmp); \ +} + +OCT_READ(8, uint8_t, "lb"); +OCT_READ(16, uint16_t, "lh"); +OCT_READ(32, uint32_t, "lw"); +OCT_READ(64, uint64_t, "ld"); +#else /* * XXX @@ -169,52 +160,117 @@ static inline int32_t oct_readint32 (uin * into XKPHYS here so that we could guarantee that interrupts were the only * kind of exception we needed to worry about. */ - -/* - * Read/write functions - */ static inline void oct_write64 (uint64_t csr_addr, uint64_t val64) { - __asm __volatile ( + uint32_t csr_addrh = csr_addr >> 32; + uint32_t csr_addrl = csr_addr; + uint32_t valh = val64 >> 32; + uint32_t vall = val64; + uint32_t tmp1; + uint32_t tmp2; + uint32_t tmp3; + + __asm __volatile ( ".set push\n" ".set mips64\n" - "sd %0, 0(%1)\n" + ".set noreorder\n" + ".set noat\n" + "dsll %0, %3, 32\n" + "dsll %1, %5, 32\n" + "dsll %2, %4, 32\n" + "dsrl %2, %2, 32\n" + "or %0, %0, %2\n" + "dsll %2, %6, 32\n" + "dsrl %2, %2, 32\n" + "or %1, %1, %2\n" + "sd %0, 0(%1)\n" ".set pop\n" - : - : "r"(val64), "r"(csr_addr)); + : "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3) + : "r" (valh), "r" (vall), "r" (csr_addrh), "r" (csr_addrl)); } -static inline void oct_write64_int64 (uint64_t csr_addr, int64_t val64i) +static inline void oct_write8_x8 (uint64_t csr_addr, uint8_t val8) { - __asm __volatile ( + uint32_t csr_addrh = csr_addr >> 32; + uint32_t csr_addrl = csr_addr; + uint32_t tmp1; + uint32_t tmp2; + + __asm __volatile ( ".set push\n" ".set mips64\n" - "sd %0, 0(%1)\n" + ".set noreorder\n" + ".set noat\n" + "dsll %0, %3, 32\n" + "dsll %1, %4, 32\n" + "dsrl %1, %1, 32\n" + "or %0, %0, %1\n" + "sb %2, 0(%0)\n" ".set pop\n" - : - : "r"(val64i), "r"(csr_addr)); + : "=&r" (tmp1), "=&r" (tmp2) + : "r" (val8), "r" (csr_addrh), "r" (csr_addrl)); } -/* - * oct_write8_x8 - * - * 8 bit data write into IO Space. Written using an 8 bit bus io transaction - */ -static inline void oct_write8_x8 (uint64_t csr_addr, uint8_t val8) +#define OCT_READ(n, t, insn) \ +static inline t oct_read ## n(uint64_t csr_addr) \ +{ \ + uint32_t csr_addrh = csr_addr >> 32; \ + uint32_t csr_addrl = csr_addr; \ + uint32_t tmp1, tmp2; \ + \ + __asm __volatile ( \ + ".set push\n" \ + ".set mips64\n" \ + ".set noreorder\n" \ + ".set noat\n" \ + "dsll %1, %2, 32\n" \ + "dsll %0, %3, 32\n" \ + "dsrl %0, %0, 32\n" \ + "or %1, %1, %0\n" \ + "lb %1, 0(%1)\n" \ + ".set pop\n" \ + : "=&r" (tmp1), "=&r" (tmp2) \ + : "r" (csr_addrh), "r" (csr_addrl)); \ + return ((t)tmp2); \ +} + +OCT_READ(8, uint8_t, "lb"); +OCT_READ(16, uint16_t, "lh"); +OCT_READ(32, uint32_t, "lw"); + +static inline uint64_t oct_read64 (uint64_t csr_addr) { - __asm __volatile ( + uint32_t csr_addrh = csr_addr >> 32; + uint32_t csr_addrl = csr_addr; + uint32_t valh; + uint32_t vall; + + __asm __volatile ( ".set push\n" ".set mips64\n" - "sb %0, 0(%1)\n" - ".set pop\n" - : - : "r"(val8), "r"(csr_addr)); + ".set noreorder\n" + ".set noat\n" + "dsll %0, %2, 32\n" + "dsll %1, %3, 32\n" + "dsrl %1, %1, 32\n" + "or %0, %0, %1\n" + "ld %1, 0(%0)\n" + "dsrl %0, %1, 32\n" + "dsll %1, %1, 32\n" + "dsrl %1, %1, 32\n" + ".set pop\n" + : "=&r" (valh), "=&r" (vall) + : "r" (csr_addrh), "r" (csr_addrl)); + return ((uint64_t)valh << 32) | vall; } +#endif + +#endif + +#define oct_write64_int64(a, v) (oct_write64(a, (int64_t)(v))) /* - * oct_write8 - * - * 8 bit data write into IO Space. Written using a 64 bit bus io transaction + * Most write bus transactions are actually 64-bit on Octeon. */ static inline void oct_write8 (uint64_t csr_addr, uint8_t val8) { @@ -231,72 +287,7 @@ static inline void oct_write32 (uint64_t oct_write64(csr_addr, (uint64_t) val32); } -static inline uint8_t oct_read8 (uint64_t csr_addr) -{ - uint64_t tmp; - - __asm __volatile ( - ".set mips64\n" - "lb %0, 0(%1)\n" - ".set mips0\n" - : "=r"(tmp) - : "r"(csr_addr)); - return ((uint8_t) tmp); -} - -static inline uint16_t oct_read16 (uint64_t csr_addr) -{ - uint64_t tmp; - - __asm __volatile ( - ".set mips64\n" - "lh %0, 0(%1)\n" - ".set mips0\n" - : "=r"(tmp) - : "r"(csr_addr)); - return ((uint16_t) tmp); -} - -static inline uint32_t oct_read32 (uint64_t csr_addr) -{ - uint64_t tmp; - - __asm __volatile ( - ".set mips64\n" - "lw %0, 0(%1)\n" - ".set mips0\n" - : "=r"(tmp) - : "r"(csr_addr)); - return ((uint32_t) tmp); -} - -static inline uint64_t oct_read64 (uint64_t csr_addr) -{ - uint64_t tmp; - - __asm __volatile ( - ".set mips64\n" - "ld %0, 0(%1)\n" - ".set mips0\n" - : "=r"(tmp) - : "r"(csr_addr)); - return (tmp); -} - -static inline int32_t oct_readint32 (uint64_t csr_addr) -{ - int32_t tmp; - - __asm __volatile ( - ".set mips64\n" - "lw %0, 0(%1)\n" - ".set mips0\n" - : "=r"(tmp) - : "r"(csr_addr)); - return ((int32_t) tmp); -} -#endif - +#define oct_readint32(a) ((int32_t)oct_read32((a))) #define OCTEON_HW_BASE ((volatile uint64_t *) 0L) #define OCTEON_REG_OFFSET (-4 * 1024ll) /* local scratchpad reg base */ @@ -452,7 +443,7 @@ typedef enum { /* PTR_SIZE == sizeof(uint32_t) */ -#ifdef __mips_n32 +#if defined(__mips_n32) || defined(__mips_o32) #define mipsx_addr_size uint32_t // u_int64 #define MIPSX_ADDR_SIZE_KSEGX_BIT_SHIFT 30 // 62 #define MIPSX_ADDR_SIZE_KSEGX_MASK_REMOVED 0x1fffffff // 0x1fffffff Added: user/jmallett/octeon/sys/mips/conf/OCTEON1-o32 ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ user/jmallett/octeon/sys/mips/conf/OCTEON1-o32 Fri Mar 5 02:52:23 2010 (r204747) @@ -0,0 +1,94 @@ +# OCTEON1 -- Configuration kernel for all Octeon1 SoCs from Cavium Networks +# +# For more information on this file, please read the handbook section on +# Kernel Configuration Files: +# +# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html +# +# The handbook is also available locally in /usr/share/doc/handbook +# if you've installed the doc distribution, otherwise always see the +# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the +# latest information. +# +# An exhaustive list of options and more detailed explanations of the +# device lines is also present in the ../../conf/NOTES and NOTES files. +# If you are in doubt as to the purpose or necessity of a line, check first +# in NOTES. +# +# $FreeBSD: user/jmallett/octeon/sys/mips/conf/OCTEON1-32 204680 2010-03-04 00:40:53Z jmallett $ + +machine mips +cpu CPU_MIPS4KC +ident OCTEON1 + +# Don't build any modules yet. +makeoptions MODULES_OVERRIDE="" +makeoptions TARGET_BIG_ENDIAN=defined +makeoptions ARCH_FLAGS="-march=mips64 -mabi=32" +makeoptions LDSCRIPT_NAME=ldscript.mips.octeon1.32 + +makeoptions KERNLOADADDR=0xffffffff81000000 + +include "../cavium/std.octeon1" + +hints "OCTEON1.hints" #Default places to look for devices. + +makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols + +options ISA_MIPS32 + +options DDB +options KDB + +options SCHED_4BSD #4BSD scheduler +options INET #InterNETworking +options NFSCLIENT #Network Filesystem Client +options NFS_ROOT #NFS usable as /, requires NFSCLIENT +options PSEUDOFS #Pseudo-filesystem framework +options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions +#options ROOTDEVNAME=\"ufs:ad0s1a\" # Original +options NO_SWAPPING + +#options BOOTP +#options BOOTP_NFSROOT +#options BOOTP_NFSV3 +#options BOOTP_COMPAT + +options FFS #Berkeley Fast Filesystem +options SOFTUPDATES #Enable FFS soft updates support +options UFS_ACL #Support for access control lists +options UFS_DIRHASH #Improve performance on big directories + + +# Debugging for use in -current +#options DEADLKRES #Enable the deadlock resolver +options INVARIANTS #Enable calls of extra sanity checking +options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS +#options WITNESS #Enable checks to detect deadlocks and cycles +#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed + +#XXXimp device genclock +device loop +device ether +device md +device uart +nodevice uart_ns8250 +device rgmii +#options VERBOSE_SYSINIT + +device bpf +device random + +# +# Use the following for Compact Flash file-system +device cf +options ROOTDEVNAME=\"ufs:cf0s1\" + +# +# Use the following for RFS in mem-device +#options MD_ROOT +#options ROOTDEVNAME = \"ufs:md0\" + +#options MD_ROOT_SIZE = 21264 +#XXX: Bring up UP first, then generalize. +#options SMP Modified: user/jmallett/octeon/sys/mips/include/_bus.h ============================================================================== --- user/jmallett/octeon/sys/mips/include/_bus.h Fri Mar 5 00:54:28 2010 (r204746) +++ user/jmallett/octeon/sys/mips/include/_bus.h Fri Mar 5 02:52:23 2010 (r204747) @@ -35,7 +35,7 @@ * Bus address and size types */ #include "opt_cputype.h" -#if defined(TARGET_OCTEON) && defined(__mips_n32) +#if defined(TARGET_OCTEON) && (defined(__mips_n32) || defined(__mips_o32)) typedef uint64_t bus_addr_t; #else typedef uintptr_t bus_addr_t; Modified: user/jmallett/octeon/sys/mips/mips/bus_space_generic.c ============================================================================== --- user/jmallett/octeon/sys/mips/mips/bus_space_generic.c Fri Mar 5 00:54:28 2010 (r204746) +++ user/jmallett/octeon/sys/mips/mips/bus_space_generic.c Fri Mar 5 02:52:23 2010 (r204747) @@ -198,7 +198,7 @@ static struct bus_space generic_space = /* Ultra-gross kludge */ #include "opt_cputype.h" -#if defined(TARGET_OCTEON) && defined(__mips_n32) +#if defined(TARGET_OCTEON) && (defined(__mips_n32) || defined(__mips_o32)) #include #define rd8(a) oct_read8(a) #define rd16(a) oct_read16(a)