Date: Sun, 24 May 2015 12:12:02 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r283365 - in head/sys/arm: arm include Message-ID: <201505241212.t4OCC2uU054606@svn.freebsd.org>
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Author: andrew Date: Sun May 24 12:12:01 2015 New Revision: 283365 URL: https://svnweb.freebsd.org/changeset/base/283365 Log: Add more cp15_ functions, and use them in cpufunc.c where possible. Modified: head/sys/arm/arm/cpufunc.c head/sys/arm/include/cpu-v6.h head/sys/arm/include/sysreg.h Modified: head/sys/arm/arm/cpufunc.c ============================================================================== --- head/sys/arm/arm/cpufunc.c Sun May 24 11:24:14 2015 (r283364) +++ head/sys/arm/arm/cpufunc.c Sun May 24 12:12:01 2015 (r283365) @@ -1116,37 +1116,20 @@ cpu_scc_setup_ccnt(void) * you want! */ #ifdef _PMC_USER_READ_WRITE_ -#if defined(CPU_ARM1176) - /* Use the Secure User and Non-secure Access Validation Control Register - * to allow userland access - */ - __asm volatile ("mcr p15, 0, %0, c15, c9, 0\n\t" - : - : "r"(0x00000001)); -#else /* Set PMUSERENR[0] to allow userland access */ - __asm volatile ("mcr p15, 0, %0, c9, c14, 0\n\t" - : - : "r"(0x00000001)); -#endif + cp15_pmuserenr_set(1); #endif #if defined(CPU_ARM1176) /* Set PMCR[2,0] to enable counters and reset CCNT */ - __asm volatile ("mcr p15, 0, %0, c15, c12, 0\n\t" - : - : "r"(0x00000005)); + cp15_pmcr_set(5); #else /* Set up the PMCCNTR register as a cyclecounter: * Set PMINTENCLR to 0xFFFFFFFF to block interrupts * Set PMCR[2,0] to enable counters and reset CCNT * Set PMCNTENSET to 0x80000000 to enable CCNT */ - __asm volatile ("mcr p15, 0, %0, c9, c14, 2\n\t" - "mcr p15, 0, %1, c9, c12, 0\n\t" - "mcr p15, 0, %2, c9, c12, 1\n\t" - : - : "r"(0xFFFFFFFF), - "r"(0x00000005), - "r"(0x80000000)); + cp15_pminten_clr(0xFFFFFFFF); + cp15_pmcr_set(5); + cp15_pmcnten_set(0x80000000); #endif } #endif @@ -1214,19 +1197,18 @@ arm11x6_setup(void) __asm volatile ("mcr\tp15, 0, %0, c7, c7, 0" : : "r"(sbz)); /* Allow detection code to find the VFP if it's fitted. */ - __asm volatile ("mcr\tp15, 0, %0, c1, c0, 2" : : "r" (0x0fffffff)); + cp15_cpacr_set(0x0fffffff); /* Set the control register */ ctrl = cpuctrl; cpu_control(~cpuctrl_wax, cpuctrl); - __asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" - "and %1, %0, %2\n\t" - "orr %1, %1, %3\n\t" - "teq %0, %1\n\t" - "mcrne p15, 0, %1, c1, c0, 1\n\t" - : "=r"(tmp), "=r"(tmp2) : - "r"(auxctrl_wax), "r"(auxctrl)); + tmp = cp15_actlr_get(); + tmp2 = tmp; + tmp &= auxctrl_wax; + tmp |= auxctrl; + if (tmp != tmp2) + cp15_actlr_set(tmp); /* And again. */ cpu_idcache_wbinv_all(); Modified: head/sys/arm/include/cpu-v6.h ============================================================================== --- head/sys/arm/include/cpu-v6.h Sun May 24 11:24:14 2015 (r283364) +++ head/sys/arm/include/cpu-v6.h Sun May 24 12:12:01 2015 (r283365) @@ -139,6 +139,8 @@ _WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0)) / /* Various control registers */ +_RF0(cp15_cpacr_get, CP15_CPACR(%0)) +_WF1(cp15_cpacr_set, CP15_CPACR(%0)) _RF0(cp15_dfsr_get, CP15_DFSR(%0)) _RF0(cp15_ifsr_get, CP15_IFSR(%0)) _WF1(cp15_prrr_set, CP15_PRRR(%0)) @@ -149,8 +151,10 @@ _RF0(cp15_dfar_get, CP15_DFAR(%0)) _RF0(cp15_ifar_get, CP15_IFAR(%0)) _RF0(cp15_l2ctlr_get, CP15_L2CTLR(%0)) #endif -#if __ARM_ARCH >= 6 +/* ARMv6+ and XScale */ _RF0(cp15_actlr_get, CP15_ACTLR(%0)) +_WF1(cp15_actlr_set, CP15_ACTLR(%0)) +#if __ARM_ARCH >= 6 _WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0)); _RF0(cp15_par_get, CP15_PAR); _RF0(cp15_sctlr_get, CP15_SCTLR(%0)) @@ -163,7 +167,10 @@ _RF0(cp15_tcmtr_get, CP15_TCMTR(%0)) _RF0(cp15_tlbtr_get, CP15_TLBTR(%0)) _RF0(cp15_mpidr_get, CP15_MPIDR(%0)) _RF0(cp15_revidr_get, CP15_REVIDR(%0)) +_RF0(cp15_ccsidr_get, CP15_CCSIDR(%0)) +_RF0(cp15_clidr_get, CP15_CLIDR(%0)) _RF0(cp15_aidr_get, CP15_AIDR(%0)) +_WF1(cp15_csselr_set, CP15_CSSELR(%0)) _RF0(cp15_id_pfr0_get, CP15_ID_PFR0(%0)) _RF0(cp15_id_pfr1_get, CP15_ID_PFR1(%0)) _RF0(cp15_id_dfr0_get, CP15_ID_DFR0(%0)) @@ -183,6 +190,10 @@ _RF0(cp15_cbar_get, CP15_CBAR(%0)) /* Performance Monitor registers */ #if __ARM_ARCH == 6 && defined(CPU_ARM1176) +_RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0)) +_WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0)) +_RF0(cp15_pmcr_get, CP15_PMCR(%0)) +_WF1(cp15_pmcr_set, CP15_PMCR(%0)) _RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0)) _WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0)) #elif __ARM_ARCH > 6 Modified: head/sys/arm/include/sysreg.h ============================================================================== --- head/sys/arm/include/sysreg.h Sun May 24 11:24:14 2015 (r283364) +++ head/sys/arm/include/sysreg.h Sun May 24 12:12:01 2015 (r283365) @@ -210,6 +210,8 @@ * CP15 C9 registers */ #if __ARM_ARCH == 6 && defined(CPU_ARM1176) +#define CP15_PMUSERENR(rr) p15, 0, rr, c15, c9, 0 /* Access Validation Control Register */ +#define CP15_PMCR(rr) p15, 0, rr, c15, c12, 0 /* Performance Monitor Control Register */ #define CP15_PMCCNTR(rr) p15, 0, rr, c15, c12, 1 /* PM Cycle Count Register */ #elif __ARM_ARCH > 6 #define CP15_L2CTLR(rr) p15, 1, rr, c9, c0, 2 /* L2 Control Register */
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