Date: Thu, 15 Jun 2017 02:45:43 +0000 (UTC) From: David C Somayajulu <davidcs@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r319964 - head/sys/dev/qlnx/qlnxe Message-ID: <201706150245.v5F2jhna021469@repo.freebsd.org>
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Author: davidcs Date: Thu Jun 15 02:45:43 2017 New Revision: 319964 URL: https://svnweb.freebsd.org/changeset/base/319964 Log: Upgrade STORMFW to 8.30.0.0 and ecore version to 8.30.0.0 Add support for pci deviceID 0x8070 for QLE41xxx product line which supports 10GbE/25GbE/40GbE MFC after:5 days Modified: head/sys/dev/qlnx/qlnxe/bcm_osal.h head/sys/dev/qlnx/qlnxe/common_hsi.h head/sys/dev/qlnx/qlnxe/ecore.h head/sys/dev/qlnx/qlnxe/ecore_chain.h head/sys/dev/qlnx/qlnxe/ecore_cxt.c head/sys/dev/qlnx/qlnxe/ecore_cxt.h head/sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c head/sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.h head/sys/dev/qlnx/qlnxe/ecore_dbg_values.h head/sys/dev/qlnx/qlnxe/ecore_dcbx.c head/sys/dev/qlnx/qlnxe/ecore_dcbx.h head/sys/dev/qlnx/qlnxe/ecore_dev.c head/sys/dev/qlnx/qlnxe/ecore_dev_api.h head/sys/dev/qlnx/qlnxe/ecore_fcoe_api.h head/sys/dev/qlnx/qlnxe/ecore_gtt_reg_addr.h head/sys/dev/qlnx/qlnxe/ecore_hsi_common.h head/sys/dev/qlnx/qlnxe/ecore_hsi_debug_tools.h head/sys/dev/qlnx/qlnxe/ecore_hsi_eth.h head/sys/dev/qlnx/qlnxe/ecore_hsi_fcoe.h head/sys/dev/qlnx/qlnxe/ecore_hsi_iscsi.h head/sys/dev/qlnx/qlnxe/ecore_hsi_iwarp.h head/sys/dev/qlnx/qlnxe/ecore_hsi_rdma.h head/sys/dev/qlnx/qlnxe/ecore_hsi_roce.h head/sys/dev/qlnx/qlnxe/ecore_hw.c head/sys/dev/qlnx/qlnxe/ecore_hw.h head/sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c head/sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.h head/sys/dev/qlnx/qlnxe/ecore_init_ops.c head/sys/dev/qlnx/qlnxe/ecore_init_ops.h head/sys/dev/qlnx/qlnxe/ecore_init_values.h head/sys/dev/qlnx/qlnxe/ecore_int.c head/sys/dev/qlnx/qlnxe/ecore_int.h head/sys/dev/qlnx/qlnxe/ecore_int_api.h head/sys/dev/qlnx/qlnxe/ecore_iov_api.h head/sys/dev/qlnx/qlnxe/ecore_iro.h head/sys/dev/qlnx/qlnxe/ecore_iro_values.h head/sys/dev/qlnx/qlnxe/ecore_iscsi.h head/sys/dev/qlnx/qlnxe/ecore_iscsi_api.h head/sys/dev/qlnx/qlnxe/ecore_l2.c head/sys/dev/qlnx/qlnxe/ecore_l2.h head/sys/dev/qlnx/qlnxe/ecore_l2_api.h head/sys/dev/qlnx/qlnxe/ecore_ll2.h head/sys/dev/qlnx/qlnxe/ecore_ll2_api.h head/sys/dev/qlnx/qlnxe/ecore_mcp.c head/sys/dev/qlnx/qlnxe/ecore_mcp.h head/sys/dev/qlnx/qlnxe/ecore_mcp_api.h head/sys/dev/qlnx/qlnxe/ecore_ooo.h head/sys/dev/qlnx/qlnxe/ecore_proto_if.h head/sys/dev/qlnx/qlnxe/ecore_roce.h head/sys/dev/qlnx/qlnxe/ecore_roce_api.h head/sys/dev/qlnx/qlnxe/ecore_rt_defs.h head/sys/dev/qlnx/qlnxe/ecore_sp_api.h head/sys/dev/qlnx/qlnxe/ecore_sp_commands.c head/sys/dev/qlnx/qlnxe/ecore_sp_commands.h head/sys/dev/qlnx/qlnxe/ecore_spq.c head/sys/dev/qlnx/qlnxe/ecore_sriov.h head/sys/dev/qlnx/qlnxe/ecore_vf.h head/sys/dev/qlnx/qlnxe/ecore_vf_api.h head/sys/dev/qlnx/qlnxe/ecore_vfpf_if.h head/sys/dev/qlnx/qlnxe/eth_common.h head/sys/dev/qlnx/qlnxe/fcoe_common.h head/sys/dev/qlnx/qlnxe/iscsi_common.h head/sys/dev/qlnx/qlnxe/mcp_private.h head/sys/dev/qlnx/qlnxe/mcp_public.h head/sys/dev/qlnx/qlnxe/mfw_hsi.h head/sys/dev/qlnx/qlnxe/nvm_cfg.h head/sys/dev/qlnx/qlnxe/nvm_map.h head/sys/dev/qlnx/qlnxe/pcics_reg_driver.h head/sys/dev/qlnx/qlnxe/qlnx_def.h head/sys/dev/qlnx/qlnxe/qlnx_os.c head/sys/dev/qlnx/qlnxe/qlnx_ver.h head/sys/dev/qlnx/qlnxe/rdma_common.h head/sys/dev/qlnx/qlnxe/reg_addr.h head/sys/dev/qlnx/qlnxe/spad_layout.h head/sys/dev/qlnx/qlnxe/storage_common.h head/sys/dev/qlnx/qlnxe/tcp_common.h Modified: head/sys/dev/qlnx/qlnxe/bcm_osal.h ============================================================================== --- head/sys/dev/qlnx/qlnxe/bcm_osal.h Thu Jun 15 02:39:33 2017 (r319963) +++ head/sys/dev/qlnx/qlnxe/bcm_osal.h Thu Jun 15 02:45:43 2017 (r319964) @@ -34,12 +34,17 @@ #include "ecore_status.h" #include <sys/bitstring.h> -#if __FreeBSD_version >= 1100090 +#if __FreeBSD_version >= 1200000 #include <linux/bitmap.h> #else +#if __FreeBSD_version >= 1100090 +#include <compat/linuxkpi/common/include/linux/bitops.h> +#else #include <ofed/include/linux/bitops.h> #endif +#endif +#define OSAL_NUM_CPUS() mp_ncpus /* * prototypes of freebsd specific functions required by ecore */ @@ -60,6 +65,7 @@ extern int qlnx_pci_find_capability(void *ecore_dev, i extern uint32_t qlnx_direct_reg_rd32(void *p_hwfn, uint32_t *reg_addr); extern void qlnx_direct_reg_wr32(void *p_hwfn, void *reg_addr, uint32_t value); +extern void qlnx_direct_reg_wr64(void *p_hwfn, void *reg_addr, uint64_t value); extern uint32_t qlnx_reg_rd32(void *p_hwfn, uint32_t reg_addr); extern void qlnx_reg_wr32(void *p_hwfn, uint32_t reg_addr, uint32_t value); @@ -129,6 +135,8 @@ rounddown_pow_of_two(unsigned long x) #endif /* #ifndef QLNX_RDMA */ +#define OSAL_UNUSED + #define OSAL_CPU_TO_BE64(val) htobe64(val) #define OSAL_BE64_TO_CPU(val) be64toh(val) @@ -199,6 +207,8 @@ typedef struct osal_list_t #define REG_WR(hwfn, addr, val) qlnx_reg_wr32(hwfn, addr, val) #define REG_WR16(hwfn, addr, val) qlnx_reg_wr16(hwfn, addr, val) #define DIRECT_REG_WR(p_hwfn, addr, value) qlnx_direct_reg_wr32(p_hwfn, addr, value) +#define DIRECT_REG_WR64(p_hwfn, addr, value) \ + qlnx_direct_reg_wr64(p_hwfn, addr, value) #define DIRECT_REG_RD(p_hwfn, addr) qlnx_direct_reg_rd32(p_hwfn, addr) #define REG_RD(hwfn, addr) qlnx_reg_rd32(hwfn, addr) #define DOORBELL(hwfn, addr, value) \ Modified: head/sys/dev/qlnx/qlnxe/common_hsi.h ============================================================================== --- head/sys/dev/qlnx/qlnxe/common_hsi.h Thu Jun 15 02:39:33 2017 (r319963) +++ head/sys/dev/qlnx/qlnxe/common_hsi.h Thu Jun 15 02:45:43 2017 (r319964) @@ -88,7 +88,7 @@ #define CORE_SPQE_PAGE_SIZE_BYTES 4096 /* - * Usually LL2 queues are opened in pairs TX-RX. + * Usually LL2 queues are opened in pairs – TX-RX. * There is a hard restriction on number of RX queues (limited by Tstorm RAM) and TX counters (Pstorm RAM). * Number of TX queues is almost unlimited. * The constants are different so as to allow asymmetric LL2 connections @@ -99,13 +99,13 @@ /////////////////////////////////////////////////////////////////////////////////////////////////// -// Include firmware version number only- do not add constants here to avoid redundunt compilations +// Include firmware verison number only- do not add constants here to avoid redundunt compilations /////////////////////////////////////////////////////////////////////////////////////////////////// #define FW_MAJOR_VERSION 8 -#define FW_MINOR_VERSION 18 -#define FW_REVISION_VERSION 14 +#define FW_MINOR_VERSION 30 +#define FW_REVISION_VERSION 0 #define FW_ENGINEERING_VERSION 0 /***********************/ @@ -113,60 +113,60 @@ /***********************/ /* PCI functions */ -#define MAX_NUM_PORTS_K2 (4) #define MAX_NUM_PORTS_BB (2) -#define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) +#define MAX_NUM_PORTS_K2 (4) +#define MAX_NUM_PORTS_E5 (MAX_NUM_PORTS_K2) +#define MAX_NUM_PORTS (MAX_NUM_PORTS_E5) -#define MAX_NUM_PFS_K2 (16) #define MAX_NUM_PFS_BB (8) -#define MAX_NUM_PFS (MAX_NUM_PFS_K2) +#define MAX_NUM_PFS_K2 (16) +#define MAX_NUM_PFS_E5 (MAX_NUM_PFS_K2) +#define MAX_NUM_PFS (MAX_NUM_PFS_E5) #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ #define MAX_NUM_VFS_BB (120) #define MAX_NUM_VFS_K2 (192) -#define E4_MAX_NUM_VFS (MAX_NUM_VFS_K2) -#define E5_MAX_NUM_VFS (240) -#define COMMON_MAX_NUM_VFS (E5_MAX_NUM_VFS) +#define MAX_NUM_VFS_E4 (MAX_NUM_VFS_K2) +#define MAX_NUM_VFS_E5 (240) +#define COMMON_MAX_NUM_VFS (MAX_NUM_VFS_E5) #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2) -#define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + E4_MAX_NUM_VFS) +#define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS_E4) /* in both BB and K2, the VF number starts from 16. so for arrays containing all */ /* possible PFs and VFs - we need a constant for this size */ #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2) -#define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + E4_MAX_NUM_VFS) +#define MAX_FUNCTION_NUMBER_E4 (MAX_NUM_PFS + MAX_NUM_VFS_E4) +#define MAX_FUNCTION_NUMBER_E5 (MAX_NUM_PFS + MAX_NUM_VFS_E5) +#define COMMON_MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS_E5) #define MAX_NUM_VPORTS_K2 (208) #define MAX_NUM_VPORTS_BB (160) -#define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) +#define MAX_NUM_VPORTS_E4 (MAX_NUM_VPORTS_K2) +#define MAX_NUM_VPORTS_E5 (256) +#define COMMON_MAX_NUM_VPORTS (MAX_NUM_VPORTS_E5) #define MAX_NUM_L2_QUEUES_K2 (320) #define MAX_NUM_L2_QUEUES_BB (256) #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ -// 4-Port K2. #define NUM_PHYS_TCS_4PORT_K2 (4) +#define NUM_PHYS_TCS_4PORT_E5 (6) #define NUM_OF_PHYS_TCS (8) - +#define PURE_LB_TC NUM_OF_PHYS_TCS #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) +#define NUM_TCS_4PORT_E5 (NUM_PHYS_TCS_4PORT_E5 + 1) #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) -#define LB_TC (NUM_OF_PHYS_TCS) - /* Num of possible traffic priority values */ #define NUM_OF_PRIO (8) -#define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2) -#define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB) -#define MAX_NUM_VOQS (MAX_NUM_VOQS_K2) -#define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB) - /* CIDs */ -#define E4_NUM_OF_CONNECTION_TYPES (8) -#define E5_NUM_OF_CONNECTION_TYPES (16) +#define NUM_OF_CONNECTION_TYPES_E4 (8) +#define NUM_OF_CONNECTION_TYPES_E5 (16) #define NUM_OF_TASK_TYPES (8) #define NUM_OF_LCIDS (320) #define NUM_OF_LTIDS (320) @@ -375,11 +375,13 @@ /* number of TX queues in the QM */ #define MAX_QM_TX_QUEUES_K2 512 #define MAX_QM_TX_QUEUES_BB 448 +#define MAX_QM_TX_QUEUES_E5 MAX_QM_TX_QUEUES_K2 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 /* number of Other queues in the QM */ #define MAX_QM_OTHER_QUEUES_BB 64 #define MAX_QM_OTHER_QUEUES_K2 128 +#define MAX_QM_OTHER_QUEUES_E5 MAX_QM_OTHER_QUEUES_K2 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 /* number of queues in a PF queue group */ @@ -413,7 +415,9 @@ #define CAU_FSM_ETH_TX 1 /* Number of Protocol Indices per Status Block */ -#define PIS_PER_SB 12 +#define PIS_PER_SB_E4 12 +#define PIS_PER_SB_E5 8 +#define MAX_PIS_PER_SB OSAL_MAX_T(u8, PIS_PER_SB_E4, PIS_PER_SB_E5) #define CAU_HC_STOPPED_STATE 3 /* fsm is stopped or not valid for this sb */ @@ -427,7 +431,8 @@ #define MAX_SB_PER_PATH_K2 (368) #define MAX_SB_PER_PATH_BB (288) -#define MAX_TOT_SB_PER_PATH MAX_SB_PER_PATH_K2 +#define MAX_SB_PER_PATH_E5 (512) +#define MAX_TOT_SB_PER_PATH MAX_SB_PER_PATH_E5 #define MAX_SB_PER_PF_MIMD 129 #define MAX_SB_PER_PF_SIMD 64 @@ -588,7 +593,7 @@ // ILT Records #define PXP_NUM_ILT_RECORDS_BB 7600 #define PXP_NUM_ILT_RECORDS_K2 11000 -#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB,PXP_NUM_ILT_RECORDS_K2) +#define MAX_NUM_ILT_RECORDS OSAL_MAX_T(u16, PXP_NUM_ILT_RECORDS_BB,PXP_NUM_ILT_RECORDS_K2) // Host Interface @@ -633,7 +638,8 @@ /******************/ /* Number of PBF command queue lines. Each line is 32B. */ -#define PBF_MAX_CMD_LINES 3328 +#define PBF_MAX_CMD_LINES_E4 3328 +#define PBF_MAX_CMD_LINES_E5 5280 /* Number of BTB blocks. Each block is 256B. */ #define BTB_MAX_BLOCKS 1440 @@ -737,8 +743,8 @@ union rdma_eqe_data */ struct malicious_vf_eqe_data { - u8 vfId /* Malicious VF ID */; - u8 errId /* Malicious VF error */; + u8 vf_id /* Malicious VF ID */; + u8 err_id /* Malicious VF error */; __le16 reserved[3]; }; @@ -747,7 +753,7 @@ struct malicious_vf_eqe_data */ struct initial_cleanup_eqe_data { - u8 vfId /* VF ID */; + u8 vf_id /* VF ID */; u8 reserved[7]; }; @@ -1059,7 +1065,7 @@ struct db_rdma_dpm_data { __le16 icid /* internal CID */; __le16 prod_val /* aggregated value to update */; - struct db_rdma_dpm_params params /* parameters passed to RDMA firmware */; + struct db_rdma_dpm_params params /* parametes passed to RDMA firmware */; }; @@ -1113,25 +1119,25 @@ enum igu_seg_access /* - * Enumeration for L3 type field of parsing_and_err_flags_union. L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according to the last-ethertype) + * Enumeration for L3 type field of parsing_and_err_flags. L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according to the last-ethertype) */ enum l3_type { - e_l3Type_unknown, - e_l3Type_ipv4, - e_l3Type_ipv6, + e_l3_type_unknown, + e_l3_type_ipv4, + e_l3_type_ipv6, MAX_L3_TYPE }; /* - * Enumeration for l4Protocol field of parsing_and_err_flags_union. L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. + * Enumeration for l4Protocol field of parsing_and_err_flags. L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. */ enum l4_protocol { - e_l4Protocol_none, - e_l4Protocol_tcp, - e_l4Protocol_udp, + e_l4_protocol_none, + e_l4_protocol_tcp, + e_l4_protocol_udp, MAX_L4_PROTOCOL }; @@ -1146,11 +1152,11 @@ struct parsing_and_err_flags #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 /* L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. (use enum l4_protocol) */ #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 -#define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 /* Set if the packet is IPv4 fragment. */ +#define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 /* Set if the packet is IPv4/IPv6 fragment. */ #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 -#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 /* Set if VLAN tag exists. Invalid if tunnel type are IP GRE or IP GENEVE. */ +#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 /* corresponds to the same 8021q tag that is selected for 8021q-tag fiel. This flag should be set if the tag appears in the packet, regardless of its value. */ #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 -#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 /* Set if L4 checksum was calculated. */ +#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 /* Set if L4 checksum was calculated. taken from the EOP descriptor. */ #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 /* Set for PTP packet. */ #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 @@ -1162,11 +1168,11 @@ struct parsing_and_err_flags #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 /* Set if GRE/VXLAN/GENEVE tunnel detected. */ #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 -#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 /* Set if VLAN tag exists in tunnel header. */ +#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 /* This flag should be set if the tag appears in the packet tunnel header, regardless of its value.. */ #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 /* Set if either tunnel-ipv4-version-mismatch or tunnel-ipv4-hdr-len-error or tunnel-ipv4-cksm is set or tunneling ipv6 ver mismatch */ #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 -#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 /* Set if GRE or VXLAN/GENEVE UDP checksum was calculated. */ +#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 /* taken from the EOP descriptor. */ #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 /* Set if tunnel L4 checksum validation failed. Valid only if tunnel L4 checksum was calculated. */ #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 @@ -1419,21 +1425,42 @@ enum rss_hash_type /* * status block structure */ -struct status_block +struct status_block_e4 { - __le16 pi_array[PIS_PER_SB]; + __le16 pi_array[PIS_PER_SB_E4]; __le32 sb_num; -#define STATUS_BLOCK_SB_NUM_MASK 0x1FF -#define STATUS_BLOCK_SB_NUM_SHIFT 0 -#define STATUS_BLOCK_ZERO_PAD_MASK 0x7F -#define STATUS_BLOCK_ZERO_PAD_SHIFT 9 -#define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF -#define STATUS_BLOCK_ZERO_PAD2_SHIFT 16 +#define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF +#define STATUS_BLOCK_E4_SB_NUM_SHIFT 0 +#define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F +#define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9 +#define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF +#define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16 __le32 prod_index; -#define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF -#define STATUS_BLOCK_PROD_INDEX_SHIFT 0 -#define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF -#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24 +#define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF +#define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0 +#define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF +#define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24 +}; + + +/* + * status block structure + */ +struct status_block_e5 +{ + __le16 pi_array[PIS_PER_SB_E5]; + __le32 sb_num; +#define STATUS_BLOCK_E5_SB_NUM_MASK 0x1FF +#define STATUS_BLOCK_E5_SB_NUM_SHIFT 0 +#define STATUS_BLOCK_E5_ZERO_PAD_MASK 0x7F +#define STATUS_BLOCK_E5_ZERO_PAD_SHIFT 9 +#define STATUS_BLOCK_E5_ZERO_PAD2_MASK 0xFFFF +#define STATUS_BLOCK_E5_ZERO_PAD2_SHIFT 16 + __le32 prod_index; +#define STATUS_BLOCK_E5_PROD_INDEX_MASK 0xFFFFFF +#define STATUS_BLOCK_E5_PROD_INDEX_SHIFT 0 +#define STATUS_BLOCK_E5_ZERO_PAD3_MASK 0xFF +#define STATUS_BLOCK_E5_ZERO_PAD3_SHIFT 24 }; Modified: head/sys/dev/qlnx/qlnxe/ecore.h ============================================================================== --- head/sys/dev/qlnx/qlnxe/ecore.h Thu Jun 15 02:39:33 2017 (r319963) +++ head/sys/dev/qlnx/qlnxe/ecore.h Thu Jun 15 02:45:43 2017 (r319964) @@ -39,8 +39,8 @@ #include "mcp_public.h" #define ECORE_MAJOR_VERSION 8 -#define ECORE_MINOR_VERSION 18 -#define ECORE_REVISION_VERSION 13 +#define ECORE_MINOR_VERSION 30 +#define ECORE_REVISION_VERSION 0 #define ECORE_ENGINEERING_VERSION 0 #define ECORE_VERSION \ @@ -110,13 +110,13 @@ do { \ #define GET_FIELD(value, name) \ (((value) >> (name##_SHIFT)) & name##_MASK) -#define ECORE_MFW_GET_FIELD(name, field) \ - (((name) & (field ## _MASK)) >> (field ## _SHIFT)) +#define GET_MFW_FIELD(name, field) \ + (((name) & (field ## _MASK)) >> (field ## _OFFSET)) -#define ECORE_MFW_SET_FIELD(name, field, value) \ +#define SET_MFW_FIELD(name, field, value) \ do { \ - (name) &= ~((field ## _MASK) << (field ## _SHIFT)); \ - (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK)); \ + (name) &= ~((field ## _MASK) << (field ## _OFFSET)); \ + (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \ } while (0) static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS) @@ -401,6 +401,11 @@ enum ecore_wol_support { ECORE_WOL_SUPPORT_PME, }; +enum ecore_db_rec_exec { + DB_REC_DRY_RUN, + DB_REC_REAL_DEAL, +}; + struct ecore_hw_info { /* PCI personality */ enum ecore_pci_personality personality; @@ -450,10 +455,7 @@ struct ecore_hw_info { #ifndef ETH_ALEN #define ETH_ALEN 6 /* @@@ TBD - define somewhere else for Windows */ #endif - unsigned char hw_mac_addr[ETH_ALEN]; - u64 node_wwn; /* For FCoE only */ - u64 port_wwn; /* For FCoE only */ u16 num_iscsi_conns; u16 num_fcoe_conns; @@ -537,6 +539,12 @@ struct ecore_qm_info { u8 num_pf_rls; }; +struct ecore_db_recovery_info { + osal_list_t list; + osal_spinlock_t lock; + u32 db_recovery_counter; +}; + struct storm_stats { u32 address; u32 len; @@ -605,6 +613,11 @@ struct ecore_hwfn { struct ecore_ptt *p_main_ptt; struct ecore_ptt *p_dpc_ptt; + /* PTP will be used only by the leading funtion. + * Usage of all PTP-apis should be synchronized as result. + */ + struct ecore_ptt *p_ptp_ptt; + struct ecore_sb_sp_info *p_sp_sb; struct ecore_sb_attn_info *p_sb_attn; @@ -661,6 +674,9 @@ struct ecore_hwfn { /* L2-related */ struct ecore_l2_info *p_l2_info; + + /* Mechanism for recovering from doorbell drop */ + struct ecore_db_recovery_info db_recovery_info; }; enum ecore_mf_mode { @@ -694,7 +710,7 @@ struct ecore_dev { #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH) #define ECORE_IS_K2(dev) ECORE_IS_AH(dev) -#define ECORE_IS_E5(dev) false +#define ECORE_IS_E5(dev) ((dev)->type == ECORE_DEV_TYPE_E5) #define ECORE_E5_MISSING_CODE OSAL_BUILD_BUG_ON(false) @@ -703,6 +719,7 @@ struct ecore_dev { #define ECORE_DEV_ID_MASK 0xff00 #define ECORE_DEV_ID_MASK_BB 0x1600 #define ECORE_DEV_ID_MASK_AH 0x8000 +#define ECORE_DEV_ID_MASK_E5 0x8100 u16 chip_num; #define CHIP_NUM_MASK 0xffff @@ -746,7 +763,7 @@ struct ecore_dev { #define CHIP_BOND_ID_SHIFT 0 u8 num_engines; - u8 num_ports_in_engines; + u8 num_ports_in_engine; u8 num_funcs_in_port; u8 path_id; @@ -836,6 +853,9 @@ struct ecore_dev { : MAX_SB_PER_PATH_K2) #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \ : MAX_NUM_PFS_K2) + +#define CRC8_TABLE_SIZE 256 + /** * @brief ecore_concrete_to_sw_fid - get the sw function id from * the concrete value. @@ -844,8 +864,7 @@ struct ecore_dev { * * @return OSAL_INLINE u8 */ -static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev, - u32 concrete_fid) +static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid) { u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); @@ -860,8 +879,8 @@ static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct return sw_fid; } -#define PURE_LB_TC 8 #define PKT_LB_TC 9 +#define MAX_NUM_VOQS_E4 20 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate); void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev, @@ -873,6 +892,7 @@ int ecore_configure_pf_min_bandwidth(struct ecore_dev void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); int ecore_device_num_engines(struct ecore_dev *p_dev); int ecore_device_num_ports(struct ecore_dev *p_dev); +int ecore_device_get_port_id(struct ecore_dev *p_dev); void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb, u8 *mac); @@ -892,6 +912,13 @@ u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf); u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid); +const char *ecore_hw_get_resc_name(enum ecore_resources res_id); + +/* doorbell recovery mechanism */ +void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn); +void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn, + enum ecore_db_rec_exec); + /* amount of resources used in qm init */ u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn); u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn); @@ -900,7 +927,5 @@ u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_ u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn); #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0]) - -const char *ecore_hw_get_resc_name(enum ecore_resources res_id); #endif /* __ECORE_H */ Modified: head/sys/dev/qlnx/qlnxe/ecore_chain.h ============================================================================== --- head/sys/dev/qlnx/qlnxe/ecore_chain.h Thu Jun 15 02:39:33 2017 (r319963) +++ head/sys/dev/qlnx/qlnxe/ecore_chain.h Thu Jun 15 02:45:43 2017 (r319964) @@ -214,6 +214,11 @@ static OSAL_INLINE u32 ecore_chain_get_cons_idx_u32(st return p_chain->u.chain32.cons_idx; } +/* FIXME: + * Should create OSALs for the below definitions. + * For Linux, replace them with the existing U16_MAX and U32_MAX, and handle + * kernel versions that lack them. + */ #define ECORE_U16_MAX ((u16)~0U) #define ECORE_U32_MAX ((u32)~0U) Modified: head/sys/dev/qlnx/qlnxe/ecore_cxt.c ============================================================================== --- head/sys/dev/qlnx/qlnxe/ecore_cxt.c Thu Jun 15 02:39:33 2017 (r319963) +++ head/sys/dev/qlnx/qlnxe/ecore_cxt.c Thu Jun 15 02:45:43 2017 (r319964) @@ -72,17 +72,7 @@ __FBSDID("$FreeBSD$"); #define TM_ELEM_SIZE 4 /* ILT constants */ -/* If for some reason, HW P size is modified to be less than 32K, - * special handling needs to be made for CDU initialization - */ -#ifdef CONFIG_ECORE_ROCE -/* For RoCE we configure to 64K to cover for RoCE max tasks 256K purpose. Can be - * optimized with resource management scheme - */ #define ILT_DEFAULT_HW_P_SIZE 4 -#else -#define ILT_DEFAULT_HW_P_SIZE 3 -#endif #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12)) #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_##cli##_##reg##_RT_OFFSET @@ -97,22 +87,22 @@ __FBSDID("$FreeBSD$"); /* connection context union */ union conn_context { - struct core_conn_context core_ctx; - struct eth_conn_context eth_ctx; - struct iscsi_conn_context iscsi_ctx; - struct fcoe_conn_context fcoe_ctx; - struct roce_conn_context roce_ctx; + struct e4_core_conn_context core_ctx; + struct e4_eth_conn_context eth_ctx; + struct e4_iscsi_conn_context iscsi_ctx; + struct e4_fcoe_conn_context fcoe_ctx; + struct e4_roce_conn_context roce_ctx; }; /* TYPE-0 task context - iSCSI, FCOE */ union type0_task_context { - struct iscsi_task_context iscsi_ctx; - struct fcoe_task_context fcoe_ctx; + struct e4_iscsi_task_context iscsi_ctx; + struct e4_fcoe_task_context fcoe_ctx; }; /* TYPE-1 task context - ROCE */ union type1_task_context { - struct rdma_task_context roce_ctx; + struct e4_rdma_task_context roce_ctx; }; struct src_ent { @@ -274,12 +264,10 @@ struct ecore_cxt_mngr { }; /* check if resources/configuration is required according to protocol type */ -static bool src_proto(struct ecore_hwfn *p_hwfn, - enum protocol_type type) +static bool src_proto(enum protocol_type type) { return type == PROTOCOLID_ISCSI || type == PROTOCOLID_FCOE || - type == PROTOCOLID_TOE || type == PROTOCOLID_IWARP; } @@ -319,14 +307,13 @@ struct ecore_src_iids { u32 per_vf_cids; }; -static void ecore_cxt_src_iids(struct ecore_hwfn *p_hwfn, - struct ecore_cxt_mngr *p_mngr, +static void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr, struct ecore_src_iids *iids) { u32 i; for (i = 0; i < MAX_CONN_TYPES; i++) { - if (!src_proto(p_hwfn, i)) + if (!src_proto(i)) continue; iids->pf_cids += p_mngr->conn_cfg[i].cid_count; @@ -346,8 +333,7 @@ struct ecore_tm_iids { u32 per_vf_tids; }; -static void ecore_cxt_tm_iids(struct ecore_hwfn *p_hwfn, - struct ecore_cxt_mngr *p_mngr, +static void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr, struct ecore_tm_iids *iids) { bool tm_vf_required = false; @@ -454,6 +440,20 @@ static struct ecore_tid_seg *ecore_cxt_tid_seg_info(st return OSAL_NULL; } +static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs) +{ + struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; + + p_mgr->srq_count = num_srqs; +} + +u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn) +{ + struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; + + return p_mgr->srq_count; +} + /* set the iids (cid/tid) count per protocol */ static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn, enum protocol_type type, @@ -779,7 +779,7 @@ enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]); ecore_cxt_qm_iids(p_hwfn, &qm_iids); - total = ecore_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids, + total = ecore_qm_pf_mem_size(qm_iids.cids, qm_iids.vf_cids, qm_iids.tids, p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs); @@ -797,7 +797,7 @@ enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct /* SRC */ p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_SRC]); - ecore_cxt_src_iids(p_hwfn, p_mngr, &src_iids); + ecore_cxt_src_iids(p_mngr, &src_iids); /* Both the PF and VFs searcher connections are stored in the per PF * database. Thus sum the PF searcher cids and all the VFs searcher @@ -822,7 +822,7 @@ enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct /* TM PF */ p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_TM]); - ecore_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids); + ecore_cxt_tm_iids(p_mngr, &tm_iids); total = tm_iids.pf_cids + tm_iids.pf_tids_total; if (total) { p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]); @@ -952,7 +952,7 @@ static enum _ecore_status_t ecore_cxt_src_t2_alloc(str if (!p_src->active) return ECORE_SUCCESS; - ecore_cxt_src_iids(p_hwfn, p_mngr, &src_iids); + ecore_cxt_src_iids(p_mngr, &src_iids); conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; total_size = conn_num * sizeof(struct src_ent); @@ -1287,7 +1287,7 @@ enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT); clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE); - /* default ILT page size for all clients is 32K */ + /* default ILT page size for all clients is 64K */ for (i = 0; i < ILT_CLI_MAX; i++) p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE; @@ -1299,7 +1299,9 @@ enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs; /* Initialize the dynamic ILT allocation mutex */ +#ifdef CONFIG_ECORE_LOCK_ALLOC OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex); +#endif OSAL_MUTEX_INIT(&p_mngr->mutex); /* Set the cxt mangr pointer priori to further allocations */ @@ -1347,7 +1349,9 @@ void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn) ecore_cid_map_free(p_hwfn); ecore_cxt_src_t2_free(p_hwfn); ecore_ilt_shadow_free(p_hwfn); +#ifdef CONFIG_ECORE_LOCK_ALLOC OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex); +#endif OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr); p_hwfn->p_cxt_mngr = OSAL_NULL; @@ -1555,7 +1559,7 @@ static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwf } } -void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn) +void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) { struct ecore_qm_info *qm_info = &p_hwfn->qm_info; struct ecore_qm_iids iids; @@ -1563,9 +1567,8 @@ void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn) OSAL_MEM_ZERO(&iids, sizeof(iids)); ecore_cxt_qm_iids(p_hwfn, &iids); - ecore_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, p_hwfn->port_id, + ecore_qm_pf_rt_init(p_hwfn, p_ptt, p_hwfn->port_id, p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port, - p_hwfn->first_on_engine, iids.cids, iids.vf_cids, iids.tids, qm_info->start_pq, qm_info->num_pqs - qm_info->num_vf_pqs, @@ -1749,7 +1752,7 @@ static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwf if (p_shdw[line].p_virt != OSAL_NULL) { SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR, - (p_shdw[line].p_phys >> 12)); + (unsigned long long)(p_shdw[line].p_phys >> 12)); DP_VERBOSE( p_hwfn, ECORE_MSG_ILT, @@ -1771,7 +1774,7 @@ static void ecore_src_init_pf(struct ecore_hwfn *p_hwf struct ecore_src_iids src_iids; OSAL_MEM_ZERO(&src_iids, sizeof(src_iids)); - ecore_cxt_src_iids(p_hwfn, p_mngr, &src_iids); + ecore_cxt_src_iids(p_mngr, &src_iids); conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; if (!conn_num) return; @@ -1817,7 +1820,7 @@ static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn u8 i; OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids)); - ecore_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids); + ecore_cxt_tm_iids(p_mngr, &tm_iids); /* @@@TBD No pre-scan for now */ @@ -1908,9 +1911,11 @@ static void ecore_prs_init_common(struct ecore_hwfn *p static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn) { struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; - struct ecore_conn_type_cfg *p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE]; + struct ecore_conn_type_cfg *p_fcoe; struct ecore_tid_seg *p_tid; + p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE]; + /* If FCoE is active set the MAX OX_ID (tid) in the Parser */ if (!p_fcoe->cid_count) return; @@ -1934,9 +1939,9 @@ void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwf ecore_prs_init_common(p_hwfn); } -void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn) +void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) { - ecore_qm_init_pf(p_hwfn); + ecore_qm_init_pf(p_hwfn, p_ptt); ecore_cm_init_pf(p_hwfn); ecore_dq_init_pf(p_hwfn); ecore_cdu_init_pf(p_hwfn); @@ -2119,20 +2124,6 @@ enum _ecore_status_t ecore_cxt_get_cid_info(struct eco return ECORE_SUCCESS; } -static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs) -{ - struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; - - p_mgr->srq_count = num_srqs; -} - -u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn) -{ - struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; - - return p_mgr->srq_count; -} - static void ecore_rdma_set_pf_params(struct ecore_hwfn *p_hwfn, struct ecore_rdma_pf_params *p_params, u32 num_tasks) @@ -2143,7 +2134,7 @@ static void ecore_rdma_set_pf_params(struct ecore_hwfn /* Override personality with rdma flavor */ num_srqs = OSAL_MIN_T(u32, ECORE_RDMA_MAX_SRQS, p_params->num_srqs); - /* The only case RDMA personality can be overridden is if NVRAM is + /* The only case RDMA personality can be overriden is if NVRAM is * configured with ETH_RDMA or if no rdma protocol was requested */ switch (p_params->rdma_protocol) { @@ -2170,8 +2161,12 @@ static void ecore_rdma_set_pf_params(struct ecore_hwfn switch (p_hwfn->hw_info.personality) { case ECORE_PCI_ETH_IWARP: - num_qps = OSAL_MIN_T(u32, IWARP_MAX_QPS, p_params->num_qps); - num_cons = num_qps; + /* Each QP requires one connection */ + num_cons = OSAL_MIN_T(u32, IWARP_MAX_QPS, p_params->num_qps); +#ifdef CONFIG_ECORE_IWARP /* required for the define */ + /* additional connections required for passive tcp handling */ + num_cons += ECORE_IWARP_PREALLOC_CNT; +#endif proto = PROTOCOLID_IWARP; p_params->roce_edpm_mode = false; break; @@ -2576,14 +2571,14 @@ enum _ecore_status_t ecore_cxt_get_task_ctx(struct eco u8 ctx_type, void **pp_task_ctx) { - struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; - struct ecore_ilt_client_cfg *p_cli; - struct ecore_ilt_cli_blk *p_seg; - struct ecore_tid_seg *p_seg_info; - u32 proto, seg; - u32 total_lines; - u32 tid_size, ilt_idx; - u32 num_tids_per_block; + struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; + struct ecore_ilt_client_cfg *p_cli; + struct ecore_tid_seg *p_seg_info; + struct ecore_ilt_cli_blk *p_seg; + u32 num_tids_per_block; + u32 tid_size, ilt_idx; + u32 total_lines; + u32 proto, seg; /* Verify the personality */ switch (p_hwfn->hw_info.personality) { Modified: head/sys/dev/qlnx/qlnxe/ecore_cxt.h ============================================================================== --- head/sys/dev/qlnx/qlnxe/ecore_cxt.h Thu Jun 15 02:39:33 2017 (r319963) +++ head/sys/dev/qlnx/qlnxe/ecore_cxt.h Thu Jun 15 02:45:43 2017 (r319964) @@ -28,7 +28,6 @@ * */ - #ifndef _ECORE_CID_ #define _ECORE_CID_ @@ -130,15 +129,17 @@ void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwf * @brief ecore_cxt_hw_init_pf - Initailze ILT and DQ, PF phase, per path. * * @param p_hwfn + * @param p_ptt */ -void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn); +void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); /** * @brief ecore_qm_init_pf - Initailze the QM PF phase, per path * * @param p_hwfn + * @param p_ptt */ -void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn); +void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); /** * @brief Reconfigures QM pf on the fly Modified: head/sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c ============================================================================== --- head/sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c Thu Jun 15 02:39:33 2017 (r319963) +++ head/sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c Thu Jun 15 02:45:43 2017 (r319964) @@ -31,7 +31,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); - #include "bcm_osal.h" #include "ecore.h" #include "ecore_hw.h" @@ -62,9 +61,6 @@ enum mem_groups { MEM_GROUP_IOR, MEM_GROUP_RAM, MEM_GROUP_BTB_RAM, - MEM_GROUP_RDIF_CTX, - MEM_GROUP_TDIF_CTX, - MEM_GROUP_CFC_MEM, MEM_GROUP_CONN_CFC_MEM, MEM_GROUP_TASK_CFC_MEM, MEM_GROUP_CAU_PI, @@ -73,6 +69,9 @@ enum mem_groups { MEM_GROUP_PBUF, MEM_GROUP_MULD_MEM, MEM_GROUP_BTB_MEM, + MEM_GROUP_RDIF_CTX, + MEM_GROUP_TDIF_CTX, + MEM_GROUP_CFC_MEM, MEM_GROUP_IGU_MEM, MEM_GROUP_IGU_MSIX, MEM_GROUP_CAU_SB, @@ -95,9 +94,6 @@ static const char* s_mem_group_names[] = { "IOR", "RAM", "BTB_RAM", - "RDIF_CTX", - "TDIF_CTX", - "CFC_MEM", "CONN_CFC_MEM", "TASK_CFC_MEM", "CAU_PI", @@ -106,6 +102,9 @@ static const char* s_mem_group_names[] = { "PBUF", "MULD_MEM", "BTB_MEM", + "RDIF_CTX", + "TDIF_CTX", + "CFC_MEM", "IGU_MEM", "IGU_MSIX", "CAU_SB", @@ -161,7 +160,7 @@ static u32 cond12(const u32 *r, const u32 *imm) { return (r[0] != r[1] && r[2] > imm[0]); } -static u32 cond3(const u32 *r, const u32 *imm) { +static u32 cond3(const u32 *r, const u32 OSAL_UNUSED *imm) { return (r[0] != r[1]); } @@ -256,7 +255,7 @@ struct storm_defs { /* Block constant definitions */ struct block_defs { const char *name; - bool has_dbg_bus[MAX_CHIP_IDS]; + bool exists[MAX_CHIP_IDS]; bool associated_to_storm; /* Valid only if associated_to_storm is true */ @@ -280,8 +279,8 @@ struct block_defs { /* Reset register definitions */ struct reset_reg_defs { u32 addr; - u32 unreset_val; bool exists[MAX_CHIP_IDS]; + u32 unreset_val[MAX_CHIP_IDS]; }; /* Debug Bus Constraint operation constant definitions */ @@ -311,8 +310,8 @@ struct rss_mem_defs { const char *mem_name; const char *type_name; u32 addr; + u32 entry_width; u32 num_entries[MAX_CHIP_IDS]; - u32 entry_width[MAX_CHIP_IDS]; }; struct vfc_ram_defs { @@ -550,7 +549,7 @@ static struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFE static struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { /* BIN_BUF_DBG_MODE_TREE */ - { (const u32 *)dbg_modes_tree_buf, OSAL_ARRAY_SIZE(dbg_modes_tree_buf)}, + { (const u32*)dbg_modes_tree_buf, OSAL_ARRAY_SIZE(dbg_modes_tree_buf)}, /* BIN_BUF_DBG_DUMP_REG */ { dump_reg, OSAL_ARRAY_SIZE(dump_reg) }, @@ -615,7 +614,7 @@ static struct chip_defs s_chip_defs[MAX_CHIP_IDS] = { /* FPGA */ { MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB } } }, - { "k2", + { "ah", *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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