Date: Sat, 12 Apr 1997 10:31:12 -0500 From: Tony Overfield <tony@dell.com> To: Michael Smith <msmith@atrad.adelaide.edu.au>, Stephen Roome <steve@visint.co.uk>, "David Langford" <langfod@dihelix.com> Cc: hackers@freebsd.org Subject: Re: 430TX ? Message-ID: <3.0.1.32.19970412103112.006b22b4@bugs.us.dell.com> In-Reply-To: <199704120440.OAA29855@genesis.atrad.adelaide.edu.au> References: <Pine.OSF.3.95.970411094154.31682B-100000@becker2.u.washington.edu>
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Somebody said: >> > While we're talking about Intel, they claim that they're focusing more on >> > memory bandwidth these days and the Pentium II has some kind of dual bus >> > architecture that makes a significant performance difference. >> >> my instructor claims they separated the cache into instruction >> cache and data-cache.....a previously 'discredited' architecture known to >> the ancients as 'harvard architecture ( howard aiken )' as opposed to the >> traditional 'von neumann' or 'princeton' architecture.... is cache space >> relatively cheap these days? The "dual bus architecture" is not related to the split I&D cache. Michael Smith said: >Split I&D cache is nothing 'discredited' (cf. Sparc, Mips, Motorola), >and full-Havard CPUs have been around all along too (all of the m68k >family, for example). > >Cache space has nothing to do with it; the basic idea is that code and >data are not normally tightly mixed (instruction operands count as >'code') and thus having seperate caches for them can be a Good Thing. > >It Intel are hailing this as some sort of 'breakthrough', then that's >just one more reason to laugh loudly at them. Every Pentium CPU that Intel has ever made, starting four or five years ago with the very first P5, has had split I&D caches, so you shouldn't laugh at Intel in this case. Of course, the win from a split I&D cache is not really related to a low ratio of instruction and data mixing. The win comes from the concurrency that it makes possible. The CPU can fetch instructions and data from the I and D caches at the *same time* with obvious performance benefits. If I recall correctly, the data cache supports two simultaneous data references, so there can be up to three cache data references in progress at any given instant. On the other hand, Intel's "dual independent bus architecture" was first put into the Pentium Pro and it refers to the separate L2 cache bus, made practical (due to the large number of signals involved) because the L2 caches were integrated. The Pentium II also has this feature, again made practical because the L2 caches are built into the processor module. This feature allows the CPU to access the L1 and L2 caches while the CPU bus is busy. Stephen Roome said: ] This is interesting, CTCM (motherboard benchmarker program) seems to tell ] me that I can get almost 56MB/s memory bandwidth. With a 66MHz bus clock ] I can't see how that this figure can improve much. 56MB/s is about half of the "correct" number. Are you sure you're interpreting the results correctly? For example, if the benchmark is measuring MOVSD performance, perhaps you're forgetting to double the numbers, since the operation is a memory copy. If your memory bandwidth really is only 56MB/s, then that's slow, not fast. ] Seeing as Intel seem ] unlikely to support a 75MHz or 83MHz bus speed then I'd love to know how ] they intend on doing this. I can't speak for Intel, but Intel says this on its www site: "In addition, the Dual Independent Bus architecture supports the evolution of today’s 66 MHz system memory bus to a 100 MHz system memory bus within the next year." David Langford said: ) What I really dont understand is why HP and ALR(?) seem to be the only ) folks doing memory busses larger than 64 bits wide. Since the CPU only has a 64 bit data bus, the extra bits are harder to take advantage of. ) One would think that a 128bit 4-way interleaved motherboard ) would really help ) the crappy memory performance of Intel CPU based systems. Today's typical system has at least 100 MB/s memory bandwidth and many systems have over 200 MB/s memory bandwidth. Since when did that become crappy? ) (That and why mohterboard makers dont put caches on Pentium Pro motherboards ) to interface the slow main memory and the faster on chip cache.) It's because of the relatively large size of the integrated L2 cache. The best way to make the system faster is to provide faster memory. An L3 cache will have very low hit rates unless it is huge (many MB). Even so, the high hit rate of the integrated L1 and L2 caches means you'll be spending lots of money optimizing the rare cases, which has an obviously poor cost/benefit ratio for most applications. - Tony - Speaking only for myself.
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