Date: Fri, 30 Jul 2010 22:07:31 GMT From: Hans Petter Selasky <hselasky@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 181620 for review Message-ID: <201007302207.o6UM7VQM043063@repoman.freebsd.org>
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http://p4web.freebsd.org/@@181620?ac=10 Change 181620 by hselasky@hselasky_laptop001 on 2010/07/30 22:06:34 USB controller (XHCI): - correct some register definitions Affected files ... .. //depot/projects/usb/src/sys/dev/usb/controller/xhcireg.h#3 edit Differences ... ==== //depot/projects/usb/src/sys/dev/usb/controller/xhcireg.h#3 (text+ko) ==== @@ -38,7 +38,7 @@ #define XHCI_CAPLENGTH 0x00 /* RO capability */ #define XHCI_RESERVED 0x01 /* Reserved */ #define XHCI_HCIVERSION 0x02 /* RO Interface version number */ -#define XHCI_HCIVERSION_1_0 0x0090 /* xHCI version 0.9 */ +#define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */ #define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */ #define XHCI_HCSPARAMS1 0x04 /* RO structual parameters 1 */ #define XHCI_HCS1_DEVSLOT_MAX(x)((x) & 0xFF) @@ -110,7 +110,7 @@ #define XHCI_CONFIG_SLOTS_MASK 0x000000FF /* RW - number of device slot enabled */ /* XHCI port status registers */ -#define XHCI_PORTSC(n) (0x400 + (0x10 * (n))) /* XHCI port status */ +#define XHCI_PORTSC(n) (0x3F0 + (0x10 * (n))) /* XHCI port status */ #define XHCI_PS_CCS 0x00000001 /* RO - current connect status */ #define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */ #define XHCI_PS_OCA 0x00000008 /* RO - over current active */ @@ -118,7 +118,7 @@ #define XHCI_PS_PLS_GET(x) (((x) >> 5) & 0xF) /* RW - port link state */ #define XHCI_PS_PLS_SET(x) (((x) & 0xF) << 5) /* RW - port link state */ #define XHCI_PS_PP 0x00000100 /* RW - port power */ -#define XHCI_PS_PORT_SPEED(x) (((x) >> 9) & 0xF) /* RO - port speed */ +#define XHCI_PS_SPEED_GET(x) (((x) >> 9) & 0xF) /* RO - port speed */ #define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */ #define XHCI_PS_PIC_SET(x) (((x) & 0x3) << 14) /* RW - port indicator */ #define XHCI_PS_LWS 0x00010000 /* RW - port link state write strobe */ @@ -134,8 +134,10 @@ #define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */ #define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable */ #define XHCI_PS_DR 0x40000000 /* RO - device removable */ -#define XHCI_PS_WPR 0x80000000 /* RW - warm port reset */ -#define XHCI_PORTPMSC(n) (0x404 + (0x10 * (n))) /* XHCI status and control */ +#define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */ +#define XHCI_PS_CLEAR 0x80FF00F7U /* command bits */ + +#define XHCI_PORTPMSC(n) (0x3F4 + (0x10 * (n))) /* XHCI status and control */ #define XHCI_PM3_U1TO_GET(x) (((x) >> 0) & 0xFF) /* RW - U1 timeout */ #define XHCI_PM3_U1TO_SET(x) (((x) & 0xFF) << 0) /* RW - U1 timeout */ #define XHCI_PM3_U2TO_GET(x) (((x) >> 8) & 0xFF) /* RW - U2 timeout */ @@ -148,9 +150,9 @@ #define XHCI_PM2_L1SLOT_GET(x) (((x) >> 8) & 0xFF) /* RW - L1 device slot */ #define XHCI_PM2_L1SLOT_SET(x) (((x) & 0xFF) << 8) /* RW - L1 device slot */ #define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */ -#define XHCI_PORTLI(n) (0x408 + (0x10 * (n))) /* XHCI port link info */ +#define XHCI_PORTLI(n) (0x3F8 + (0x10 * (n))) /* XHCI port link info */ #define XHCI_PLI3_ERR_GET(x) (((x) >> 0) & 0xFFFF) /* RO - port link errors */ -#define XHCI_PORTRSV(n) (0x40C + (0x10 * (n))) /* XHCI port reserved */ +#define XHCI_PORTRSV(n) (0x3FC + (0x10 * (n))) /* XHCI port reserved */ /* XHCI runtime registers. Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers */ #define XHCI_MFINDEX 0x0000 /* RO - microframe index */
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