Date: Sun, 11 Apr 2010 15:35:18 +0000 (UTC) From: Marius Strobl <marius@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r206480 - head/sys/sparc64/include Message-ID: <201004111535.o3BFZIs8038127@svn.freebsd.org>
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Author: marius Date: Sun Apr 11 15:35:17 2010 New Revision: 206480 URL: http://svn.freebsd.org/changeset/base/206480 Log: Update for UltraSPARC-IV{,+} and SPARC64 V, VI, VII and VIIIfx CPUs. Modified: head/sys/sparc64/include/lsu.h Modified: head/sys/sparc64/include/lsu.h ============================================================================== --- head/sys/sparc64/include/lsu.h Sun Apr 11 15:31:09 2010 (r206479) +++ head/sys/sparc64/include/lsu.h Sun Apr 11 15:35:17 2010 (r206480) @@ -29,7 +29,7 @@ /* * Definitions for the Load-Store-Unit Control Register. This is called - * Data Cache Unit Control Register (DCUCR) for UltraSPARC-III. + * Data Cache Unit Control Register (DCUCR) for UltraSPARC-III and greater. */ #define LSU_IC (1UL << 0) #define LSU_DC (1UL << 1) @@ -41,7 +41,7 @@ #define LSU_FM_BITS 16 #define LSU_FM_MASK (((1UL << LSU_FM_BITS) - 1) << LSU_FM_SHIFT) -#define LSU_VM_SHIFT 25 +#define LSU_VM_SHIFT 25 #define LSU_VM_BITS 8 #define LSU_VM_MASK (((1UL << LSU_VM_BITS) - 1) << LSU_VM_SHIFT) @@ -65,4 +65,22 @@ #define LSU_CV (1UL << 48) #define LSU_CP (1UL << 49) +/* The following bit is valid for the UltraSPARC-IV only. */ +#define LSU_WIH (1UL << 4) + +/* The following bits are valid for the UltraSPARC-IV+ only. */ +#define LSU_PPS_SHIFT 50 +#define LSU_PPS_BITS 2 +#define LSU_PPS_MASK (((1UL << LSU_PPS_BITS) - 1) << LSU_PPS_SHIFT) + +#define LSU_IPS_SHIFT 52 +#define LSU_IPS_BITS 2 +#define LSU_IPS_MASK (((1UL << LSU_IPS_BITS) - 1) << LSU_IPS_SHIFT) + +#define LSU_PCM (1UL << 54) +#define LSU_WCE (1UL << 55) + +/* The following bit is valid for the SPARC64 V, VI, VII and VIIIfx only. */ +#define LSU_WEAK_SPCA (1UL << 41) + #endif /* _MACHINE_LSU_H_ */
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