Date: Wed, 30 Aug 1995 13:01:03 -0700 (PDT) From: "Rodney W. Grimes" <rgrimes@gndrsh.aac.dev.com> To: marino.ladavac@aut.alcatel.at Cc: hardware@freebsd.org Subject: Re: Upgrade to my machine Message-ID: <199508302001.NAA09303@gndrsh.aac.dev.com> In-Reply-To: <9508301925.AA14125@atuhc16.aut.alcatel.at> from "marino.ladavac@aut.alcatel.at" at Aug 30, 95 09:25:41 pm
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> > Rod Grimes wrote: > > > 16k of static sram takes >768K transistors assuming a 6 transistor cell, > > now perhaps the cache is done in quasi-static 4 cell cmos sram, but then > > how do they do stop clock ??? Perhaps the cache is invalidated when > > coming out of stop clock mode, or maybe that is what happens during the > > cycles it takes to shut down. > > But is it really static? I seem to recollect that original '486 could > not change clock rate on the fly, unlike '386 (allegedly, for some on > chip dynamic storage problems.) Not possitive on the true staticness of it. Though the 486 can not change clock rates, the SL enhance 486 can, as well as all Pentiums. This is the clock stop SL/enhancement features. To change clock frequencies you do a stop clock, shut the clock clear down, the start the clock up at the new frequency. > > Furthermore, since the L1 cache is on the same chip with the rest of the > CPU, refresh can be done completely transparently in the cycles when > cache is not read/written to. However, I do not know if there are such > spare cycles in Pentium case; there should be some at '486. I am pretty sure they are not fully dynamic, thus they do not require refresh, as fully dynamic would mean having to do a write back cycle after the destructive read that dynamic memory cells use. (You dump the stored charge of the cell into the bit line when you read a DRAM cell). > > Also the claims that the RISC core of the 486 is in excess of a million > > transistors in the 1994 data book sets makes me wonder how one could do > > 2 of these for the dual issue super scaler pipe in anything less than > > 2 million transistors. > > I cannot argue about that as I'm not familiar with the document, but some > manufacturers (e.g. Motorola, TI) use the word 'core' when they refer to > the sillicon part of an IC. This, and knowing that Intel's DX4 has 16K > cache on chip, it doesn't sound too impossible. My sighted data was for the 486DX2, not the 486DX4, sorry for leaving that detail out (I thought I had it in there, but above it appears missing :-(). > > Now we need to add in the MMU, TLB, and BIU to my already almost 2.7 Million > > transistors, okay, 600K transistors, 200K gates, yea, I suppose I might > > squeeze it into that... oh, and the microcode, that must be atleast > > 80 bits by 4k deep, but thats not much given ROM is 1 transistor per bit, > > plus decoders (and 4k decoderes aren't much when you use TGMX's :-)) > > > Perhaps the 3.3 million transistor count is the RISC super scaler core > > excluding the cache, MMU, TLB and BIU _and_ microcode. > > > I don't directly consult for the processor group at Intel so I don't have > > ready access to the right data. Published data like this is unclear as > > to exactly what it is. > > Well, a rough guess can be made from the die size and the manufacturing > process. This way one could get the high limit (connections ignored in > favor of transistors.) > > The die is, what, 11 mm by 10 mm? Not noted in the data books, not avaliable in die form :-(. > Process is .35 micron? A80502-60 and 66 are 5V 0.8 micron technology sporting ``3.1M transistors'' A80502-75/90/100 are 3.3V 0.6 micron technology sporting ``3.3M transistors'' > Let's say > that a 3x3 grid can house a transistor (can it? I have no idea) then > you can put cca. 1 million of them onto 1 square mm. There is about > 110 square mm of area available. Smallest transistor I could build with 0.6 micron technology is 1.8 micron by 1.2 micron, and that is assuming multiple transistors in the same well, quite common in cmos logic design. -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Reliable computers for FreeBSD
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