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Date:      Sat, 17 Apr 2010 23:04:57 +0000 (UTC)
From:      Juli Mallett <jmallett@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-user@freebsd.org
Subject:   svn commit: r206778 - in user/jmallett/octeon/sys/mips: cavium include
Message-ID:  <201004172304.o3HN4va7097918@svn.freebsd.org>

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Author: jmallett
Date: Sat Apr 17 23:04:56 2010
New Revision: 206778
URL: http://svn.freebsd.org/changeset/base/206778

Log:
  Make coprocessor 0 register with selector accessors take a name to be used
  unadulterated rather than adding the selector as a suffix.  "prid1" doesn't
  make half as much sense as "ebase".
  
  Probably other registers with selectors could use their ISA-given name here,
  too, but I don't know them.
  
  Remove a local mips_wr_ebase() from the Octeon code now that we DTRT.

Modified:
  user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c
  user/jmallett/octeon/sys/mips/cavium/octeon_mp.c
  user/jmallett/octeon/sys/mips/include/cpufunc.h

Modified: user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c	Sat Apr 17 23:04:42 2010	(r206777)
+++ user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c	Sat Apr 17 23:04:56 2010	(r206778)
@@ -86,16 +86,6 @@ static void octeon_boot_params_init(regi
 static uint64_t ciu_get_intr_sum_reg_addr(int core_num, int intx, int enx);
 static uint64_t ciu_get_intr_en_reg_addr(int core_num, int intx, int enx);
 
-static __inline void
-mips_wr_ebase(u_int32_t a0)
-{
-	__asm __volatile("mtc0 %[a0], $15, 1 ;"
-	    :
-	    :     [a0] "r"(a0));
-
-	mips_barrier();
-}
-
 void
 platform_cpu_init()
 {

Modified: user/jmallett/octeon/sys/mips/cavium/octeon_mp.c
==============================================================================
--- user/jmallett/octeon/sys/mips/cavium/octeon_mp.c	Sat Apr 17 23:04:42 2010	(r206777)
+++ user/jmallett/octeon/sys/mips/cavium/octeon_mp.c	Sat Apr 17 23:04:56 2010	(r206778)
@@ -69,7 +69,7 @@ platform_init_ap(int cpuid)
 	/*
 	 * Set the exception base.
 	 */
-	mips_wr_prid1(0x80000000 | cpuid);
+	mips_wr_ebase(0x80000000 | cpuid);
 
 	/*
 	 * Set up interrupts, clear IPIs and unmask the IPI interrupt.

Modified: user/jmallett/octeon/sys/mips/include/cpufunc.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/cpufunc.h	Sat Apr 17 23:04:42 2010	(r206777)
+++ user/jmallett/octeon/sys/mips/include/cpufunc.h	Sat Apr 17 23:04:56 2010	(r206778)
@@ -166,7 +166,7 @@ mips_wr_ ## n (uint32_t a0)					\
 
 #define	MIPS_RDRW32_COP0_SEL(n,r,s)					\
 static __inline uint32_t					\
-mips_rd_ ## n ## s(void)						\
+mips_rd_ ## n(void)						\
 {								\
 	int v0;							\
 	__asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";"	\
@@ -175,7 +175,7 @@ mips_rd_ ## n ## s(void)						\
 	return (v0);						\
 }								\
 static __inline void						\
-mips_wr_ ## n ## s(uint32_t a0)					\
+mips_wr_ ## n(uint32_t a0)					\
 {								\
 	__asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";"	\
 			 __XSTRING(COP0_SYNC)";"		\
@@ -201,9 +201,9 @@ static __inline void mips_sync_icache (v
 
 MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE);
 MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG);
-MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 1);
-MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 2);
-MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 3);
+MIPS_RDRW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1);
+MIPS_RDRW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2);
+MIPS_RDRW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3);
 MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT);
 MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX);
 MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED);
@@ -219,20 +219,20 @@ MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TL
 #endif
 MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID);
 /* XXX 64-bit?  */
-MIPS_RDRW32_COP0_SEL(prid, MIPS_COP_0_PRID, 1);
+MIPS_RDRW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1);
 MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
-MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 1);
-MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 2);
-MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 3);
+MIPS_RDRW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1);
+MIPS_RDRW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2);
+MIPS_RDRW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3);
 MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI);
-MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 1);
-MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 2);
-MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 3);
-
-MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 0);
-MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 1);
-MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 2);
-MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 3);
+MIPS_RDRW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1);
+MIPS_RDRW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2);
+MIPS_RDRW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3);
+
+MIPS_RDRW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0);
+MIPS_RDRW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1);
+MIPS_RDRW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2);
+MIPS_RDRW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3);
 
 #undef	MIPS_RDRW32_COP0
 



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