Date: Wed, 29 May 2019 20:45:31 +0000 (UTC) From: John Baldwin <jhb@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r348371 - stable/11/usr.sbin/bhyve Message-ID: <201905292045.x4TKjVVZ040848@repo.freebsd.org>
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Author: jhb Date: Wed May 29 20:45:31 2019 New Revision: 348371 URL: https://svnweb.freebsd.org/changeset/base/348371 Log: MFC 345158: Fix uart emulation bug THRE is always asserted in LSR reads, so REG_IER writes that raise IER_ETXRDY must also set thre_int_pending. Approved by: re (gjb) Modified: stable/11/usr.sbin/bhyve/uart_emul.c Directory Properties: stable/11/ (props changed) Modified: stable/11/usr.sbin/bhyve/uart_emul.c ============================================================================== --- stable/11/usr.sbin/bhyve/uart_emul.c Wed May 29 20:34:35 2019 (r348370) +++ stable/11/usr.sbin/bhyve/uart_emul.c Wed May 29 20:45:31 2019 (r348371) @@ -430,6 +430,9 @@ uart_write(struct uart_softc *sc, int offset, uint8_t sc->thre_int_pending = true; break; case REG_IER: + /* Set pending when IER_ETXRDY is raised (edge-triggered). */ + if ((sc->ier & IER_ETXRDY) == 0 && (value & IER_ETXRDY) != 0) + sc->thre_int_pending = true; /* * Apply mask so that bits 4-7 are 0 * Also enables bits 0-3 only if they're 1
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