Date: Tue, 8 Aug 2017 16:52:53 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r322259 - in vendor/llvm/dist: bindings/ocaml/llvm cmake/modules docs include/llvm/Analysis include/llvm/CodeGen lib/Analysis lib/CodeGen lib/CodeGen/SelectionDAG lib/IR lib/Object lib/... Message-ID: <201708081652.v78Gqre2082459@repo.freebsd.org>
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Author: dim Date: Tue Aug 8 16:52:53 2017 New Revision: 322259 URL: https://svnweb.freebsd.org/changeset/base/322259 Log: Vendor import of llvm release_50 branch r310316: https://llvm.org/svn/llvm-project/llvm/branches/release_50@310316 Added: vendor/llvm/dist/test/CodeGen/Mips/cconv/pr33883.ll vendor/llvm/dist/test/CodeGen/Mips/pr33978.ll vendor/llvm/dist/test/CodeGen/X86/conditional-tailcall-samedest.mir vendor/llvm/dist/test/CodeGen/X86/pause.ll vendor/llvm/dist/test/CodeGen/X86/tail-call-mutable-memarg.ll vendor/llvm/dist/test/Instrumentation/AddressSanitizer/force-dynamic-shadow.ll vendor/llvm/dist/test/Transforms/InstSimplify/pr33957.ll vendor/llvm/dist/test/Transforms/SCCP/definite-initializer.ll Modified: vendor/llvm/dist/bindings/ocaml/llvm/llvm.ml vendor/llvm/dist/bindings/ocaml/llvm/llvm.mli vendor/llvm/dist/bindings/ocaml/llvm/llvm_ocaml.c vendor/llvm/dist/cmake/modules/AddOCaml.cmake vendor/llvm/dist/docs/ReleaseNotes.rst vendor/llvm/dist/include/llvm/Analysis/ValueTracking.h vendor/llvm/dist/include/llvm/CodeGen/MachineFunction.h vendor/llvm/dist/include/llvm/CodeGen/MachineInstr.h vendor/llvm/dist/lib/Analysis/ValueTracking.cpp vendor/llvm/dist/lib/CodeGen/BranchFolding.cpp vendor/llvm/dist/lib/CodeGen/MachineFunction.cpp vendor/llvm/dist/lib/CodeGen/MachineInstr.cpp vendor/llvm/dist/lib/CodeGen/ScheduleDAGInstrs.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp vendor/llvm/dist/lib/CodeGen/StackColoring.cpp vendor/llvm/dist/lib/IR/ConstantFold.cpp vendor/llvm/dist/lib/Object/COFFImportFile.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64InstrInfo.td vendor/llvm/dist/lib/Target/AArch64/AArch64MacroFusion.cpp vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp vendor/llvm/dist/lib/Target/X86/X86InstrSSE.td vendor/llvm/dist/lib/Transforms/IPO/ArgumentPromotion.cpp vendor/llvm/dist/lib/Transforms/Instrumentation/AddressSanitizer.cpp vendor/llvm/dist/lib/Transforms/Scalar/SCCP.cpp vendor/llvm/dist/lib/Transforms/Utils/CloneModule.cpp vendor/llvm/dist/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll vendor/llvm/dist/test/CodeGen/AArch64/misched-fusion-aes.ll vendor/llvm/dist/test/CodeGen/AArch64/tbi.ll vendor/llvm/dist/test/CodeGen/AArch64/win64_vararg.ll vendor/llvm/dist/test/DllTool/coff-weak-exports.def vendor/llvm/dist/test/Instrumentation/AddressSanitizer/stack-poisoning-byval-args.ll vendor/llvm/dist/test/MC/AArch64/arm64-crypto.s vendor/llvm/dist/test/Transforms/ArgumentPromotion/byval.ll vendor/llvm/dist/unittests/Transforms/Utils/Cloning.cpp Modified: vendor/llvm/dist/bindings/ocaml/llvm/llvm.ml ============================================================================== --- vendor/llvm/dist/bindings/ocaml/llvm/llvm.ml Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/bindings/ocaml/llvm/llvm.ml Tue Aug 8 16:52:53 2017 (r322259) @@ -20,6 +20,10 @@ type llattribute type llmemorybuffer type llmdkind +exception FeatureDisabled of string + +let () = Callback.register_exception "Llvm.FeatureDisabled" (FeatureDisabled "") + module TypeKind = struct type t = | Void Modified: vendor/llvm/dist/bindings/ocaml/llvm/llvm.mli ============================================================================== --- vendor/llvm/dist/bindings/ocaml/llvm/llvm.mli Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/bindings/ocaml/llvm/llvm.mli Tue Aug 8 16:52:53 2017 (r322259) @@ -371,6 +371,8 @@ type ('a, 'b) llrev_pos = (** {6 Exceptions} *) +exception FeatureDisabled of string + exception IoError of string Modified: vendor/llvm/dist/bindings/ocaml/llvm/llvm_ocaml.c ============================================================================== --- vendor/llvm/dist/bindings/ocaml/llvm/llvm_ocaml.c Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/bindings/ocaml/llvm/llvm_ocaml.c Tue Aug 8 16:52:53 2017 (r322259) @@ -336,7 +336,12 @@ CAMLprim LLVMContextRef llvm_type_context(LLVMTypeRef /* lltype -> unit */ CAMLprim value llvm_dump_type(LLVMTypeRef Val) { +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) LLVMDumpType(Val); +#else + caml_raise_with_arg(*caml_named_value("Llvm.FeatureDisabled"), + caml_copy_string("dump")); +#endif return Val_unit; } Modified: vendor/llvm/dist/cmake/modules/AddOCaml.cmake ============================================================================== --- vendor/llvm/dist/cmake/modules/AddOCaml.cmake Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/cmake/modules/AddOCaml.cmake Tue Aug 8 16:52:53 2017 (r322259) @@ -87,6 +87,11 @@ function(add_ocaml_library name) foreach( include_dir ${LLVM_INCLUDE_DIR} ${LLVM_MAIN_INCLUDE_DIR} ) set(c_flags "${c_flags} -I${include_dir}") endforeach() + # include -D/-UNDEBUG to match dump function visibility + # regex from HandleLLVMOptions.cmake + string(REGEX MATCH "(^| )[/-][UD] *NDEBUG($| )" flag_matches + "${CMAKE_C_FLAGS_${uppercase_CMAKE_BUILD_TYPE}} ${CMAKE_C_FLAGS}") + set(c_flags "${c_flags} ${flag_matches}") foreach( ocaml_file ${ARG_OCAML} ) list(APPEND sources "${ocaml_file}.mli" "${ocaml_file}.ml") @@ -199,7 +204,7 @@ function(add_ocaml_library name) PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE GROUP_READ GROUP_EXECUTE WORLD_READ WORLD_EXECUTE - DESTINATION "${LLVM_OCAML_INSTALL_PATH}/llvm") + DESTINATION "${LLVM_OCAML_INSTALL_PATH}/stublibs") foreach( install_file ${install_files} ${install_shlibs} ) get_filename_component(filename "${install_file}" NAME) Modified: vendor/llvm/dist/docs/ReleaseNotes.rst ============================================================================== --- vendor/llvm/dist/docs/ReleaseNotes.rst Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/docs/ReleaseNotes.rst Tue Aug 8 16:52:53 2017 (r322259) @@ -125,7 +125,22 @@ Changes to the AMDGPU Target Changes to the AVR Target ----------------------------- - During this release ... +This release consists mainly of bugfixes and implementations of features +required for compiling basic Rust programs. + +* Enable the branch relaxation pass so that we don't crash on large + stack load/stores + +* Add support for lowering bit-rotations to the native `ror` and `rol` + instructions + +* Fix bug where function pointers were treated as pointers to RAM and not + pointers to program memory + +* Fix broken code generaton for shift-by-variable expressions + +* Support zero-sized types in argument lists; this is impossible in C, + but possible in Rust Changes to the OCaml bindings ----------------------------- Modified: vendor/llvm/dist/include/llvm/Analysis/ValueTracking.h ============================================================================== --- vendor/llvm/dist/include/llvm/Analysis/ValueTracking.h Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/include/llvm/Analysis/ValueTracking.h Tue Aug 8 16:52:53 2017 (r322259) @@ -312,6 +312,12 @@ template <typename T> class ArrayRef; const DataLayout &DL, LoopInfo *LI = nullptr, unsigned MaxLookup = 6); + /// This is a wrapper around GetUnderlyingObjects and adds support for basic + /// ptrtoint+arithmetic+inttoptr sequences. + void getUnderlyingObjectsForCodeGen(const Value *V, + SmallVectorImpl<Value *> &Objects, + const DataLayout &DL); + /// Return true if the only users of this pointer are lifetime markers. bool onlyUsedByLifetimeMarkers(const Value *V); Modified: vendor/llvm/dist/include/llvm/CodeGen/MachineFunction.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/MachineFunction.h Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/include/llvm/CodeGen/MachineFunction.h Tue Aug 8 16:52:53 2017 (r322259) @@ -661,6 +661,12 @@ class MachineFunction { (public) MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO, int64_t Offset, uint64_t Size); + /// Allocate a new MachineMemOperand by copying an existing one, + /// replacing only AliasAnalysis information. MachineMemOperands are owned + /// by the MachineFunction and need not be explicitly deallocated. + MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO, + const AAMDNodes &AAInfo); + using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity; /// Allocate an array of MachineOperands. This is only intended for use by Modified: vendor/llvm/dist/include/llvm/CodeGen/MachineInstr.h ============================================================================== --- vendor/llvm/dist/include/llvm/CodeGen/MachineInstr.h Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/include/llvm/CodeGen/MachineInstr.h Tue Aug 8 16:52:53 2017 (r322259) @@ -379,6 +379,9 @@ class MachineInstr (public) return NumMemRefs == 1; } + /// Return the number of memory operands. + unsigned getNumMemOperands() const { return NumMemRefs; } + /// API for querying MachineInstr properties. They are the same as MCInstrDesc /// queries but they are bundle aware. Modified: vendor/llvm/dist/lib/Analysis/ValueTracking.cpp ============================================================================== --- vendor/llvm/dist/lib/Analysis/ValueTracking.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/Analysis/ValueTracking.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -3277,6 +3277,69 @@ void llvm::GetUnderlyingObjects(Value *V, SmallVectorI } while (!Worklist.empty()); } +/// This is the function that does the work of looking through basic +/// ptrtoint+arithmetic+inttoptr sequences. +static const Value *getUnderlyingObjectFromInt(const Value *V) { + do { + if (const Operator *U = dyn_cast<Operator>(V)) { + // If we find a ptrtoint, we can transfer control back to the + // regular getUnderlyingObjectFromInt. + if (U->getOpcode() == Instruction::PtrToInt) + return U->getOperand(0); + // If we find an add of a constant, a multiplied value, or a phi, it's + // likely that the other operand will lead us to the base + // object. We don't have to worry about the case where the + // object address is somehow being computed by the multiply, + // because our callers only care when the result is an + // identifiable object. + if (U->getOpcode() != Instruction::Add || + (!isa<ConstantInt>(U->getOperand(1)) && + Operator::getOpcode(U->getOperand(1)) != Instruction::Mul && + !isa<PHINode>(U->getOperand(1)))) + return V; + V = U->getOperand(0); + } else { + return V; + } + assert(V->getType()->isIntegerTy() && "Unexpected operand type!"); + } while (true); +} + +/// This is a wrapper around GetUnderlyingObjects and adds support for basic +/// ptrtoint+arithmetic+inttoptr sequences. +void llvm::getUnderlyingObjectsForCodeGen(const Value *V, + SmallVectorImpl<Value *> &Objects, + const DataLayout &DL) { + SmallPtrSet<const Value *, 16> Visited; + SmallVector<const Value *, 4> Working(1, V); + do { + V = Working.pop_back_val(); + + SmallVector<Value *, 4> Objs; + GetUnderlyingObjects(const_cast<Value *>(V), Objs, DL); + + for (Value *V : Objs) { + if (!Visited.insert(V).second) + continue; + if (Operator::getOpcode(V) == Instruction::IntToPtr) { + const Value *O = + getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0)); + if (O->getType()->isPointerTy()) { + Working.push_back(O); + continue; + } + } + // If GetUnderlyingObjects fails to find an identifiable object, + // getUnderlyingObjectsForCodeGen also fails for safety. + if (!isIdentifiedObject(V)) { + Objects.clear(); + return; + } + Objects.push_back(const_cast<Value *>(V)); + } + } while (!Working.empty()); +} + /// Return true if the only users of this pointer are lifetime markers. bool llvm::onlyUsedByLifetimeMarkers(const Value *V) { for (const User *U : V->users()) { Modified: vendor/llvm/dist/lib/CodeGen/BranchFolding.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/BranchFolding.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/CodeGen/BranchFolding.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -1475,13 +1475,14 @@ ReoptimizeBlock: bool PredAnalyzable = !TII->analyzeBranch(*Pred, PredTBB, PredFBB, PredCond, true); - if (PredAnalyzable && !PredCond.empty() && PredTBB == MBB) { + if (PredAnalyzable && !PredCond.empty() && PredTBB == MBB && + PredTBB != PredFBB) { // The predecessor has a conditional branch to this block which consists // of only a tail call. Try to fold the tail call into the conditional // branch. if (TII->canMakeTailCallConditional(PredCond, TailCall)) { // TODO: It would be nice if analyzeBranch() could provide a pointer - // to the branch insturction so replaceBranchWithTailCall() doesn't + // to the branch instruction so replaceBranchWithTailCall() doesn't // have to search for it. TII->replaceBranchWithTailCall(*Pred, PredCond, TailCall); ++NumTailCalls; Modified: vendor/llvm/dist/lib/CodeGen/MachineFunction.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/MachineFunction.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/CodeGen/MachineFunction.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -330,6 +330,20 @@ MachineFunction::getMachineMemOperand(const MachineMem MMO->getOrdering(), MMO->getFailureOrdering()); } +MachineMemOperand * +MachineFunction::getMachineMemOperand(const MachineMemOperand *MMO, + const AAMDNodes &AAInfo) { + MachinePointerInfo MPI = MMO->getValue() ? + MachinePointerInfo(MMO->getValue(), MMO->getOffset()) : + MachinePointerInfo(MMO->getPseudoValue(), MMO->getOffset()); + + return new (Allocator) + MachineMemOperand(MPI, MMO->getFlags(), MMO->getSize(), + MMO->getBaseAlignment(), AAInfo, + MMO->getRanges(), MMO->getSyncScopeID(), + MMO->getOrdering(), MMO->getFailureOrdering()); +} + MachineInstr::mmo_iterator MachineFunction::allocateMemRefsArray(unsigned long Num) { return Allocator.Allocate<MachineMemOperand *>(Num); Modified: vendor/llvm/dist/lib/CodeGen/MachineInstr.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/MachineInstr.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/CodeGen/MachineInstr.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -578,10 +578,8 @@ bool MachinePointerInfo::isDereferenceable(unsigned Si if (BasePtr == nullptr) return false; - return isDereferenceableAndAlignedPointer(BasePtr, 1, - APInt(DL.getPointerSize(), - Offset + Size), - DL); + return isDereferenceableAndAlignedPointer( + BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL); } /// getConstantPool - Return a MachinePointerInfo record that refers to the Modified: vendor/llvm/dist/lib/CodeGen/ScheduleDAGInstrs.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/ScheduleDAGInstrs.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/CodeGen/ScheduleDAGInstrs.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -121,63 +121,6 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction & SchedModel.init(ST.getSchedModel(), &ST, TII); } -/// This is the function that does the work of looking through basic -/// ptrtoint+arithmetic+inttoptr sequences. -static const Value *getUnderlyingObjectFromInt(const Value *V) { - do { - if (const Operator *U = dyn_cast<Operator>(V)) { - // If we find a ptrtoint, we can transfer control back to the - // regular getUnderlyingObjectFromInt. - if (U->getOpcode() == Instruction::PtrToInt) - return U->getOperand(0); - // If we find an add of a constant, a multiplied value, or a phi, it's - // likely that the other operand will lead us to the base - // object. We don't have to worry about the case where the - // object address is somehow being computed by the multiply, - // because our callers only care when the result is an - // identifiable object. - if (U->getOpcode() != Instruction::Add || - (!isa<ConstantInt>(U->getOperand(1)) && - Operator::getOpcode(U->getOperand(1)) != Instruction::Mul && - !isa<PHINode>(U->getOperand(1)))) - return V; - V = U->getOperand(0); - } else { - return V; - } - assert(V->getType()->isIntegerTy() && "Unexpected operand type!"); - } while (true); -} - -/// This is a wrapper around GetUnderlyingObjects and adds support for basic -/// ptrtoint+arithmetic+inttoptr sequences. -static void getUnderlyingObjects(const Value *V, - SmallVectorImpl<Value *> &Objects, - const DataLayout &DL) { - SmallPtrSet<const Value *, 16> Visited; - SmallVector<const Value *, 4> Working(1, V); - do { - V = Working.pop_back_val(); - - SmallVector<Value *, 4> Objs; - GetUnderlyingObjects(const_cast<Value *>(V), Objs, DL); - - for (Value *V : Objs) { - if (!Visited.insert(V).second) - continue; - if (Operator::getOpcode(V) == Instruction::IntToPtr) { - const Value *O = - getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0)); - if (O->getType()->isPointerTy()) { - Working.push_back(O); - continue; - } - } - Objects.push_back(const_cast<Value *>(V)); - } - } while (!Working.empty()); -} - /// If this machine instr has memory reference information and it can be tracked /// to a normal reference to a known object, return the Value for that object. static void getUnderlyingObjectsForInstr(const MachineInstr *MI, @@ -208,12 +151,10 @@ static void getUnderlyingObjectsForInstr(const Machine Objects.push_back(UnderlyingObjectsVector::value_type(PSV, MayAlias)); } else if (const Value *V = MMO->getValue()) { SmallVector<Value *, 4> Objs; - getUnderlyingObjects(V, Objs, DL); + getUnderlyingObjectsForCodeGen(V, Objs, DL); for (Value *V : Objs) { - if (!isIdentifiedObject(V)) - return false; - + assert(isIdentifiedObject(V)); Objects.push_back(UnderlyingObjectsVector::value_type(V, true)); } } else Modified: vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -99,6 +99,27 @@ LimitFPPrecision("limit-float-precision", // store [4096 x i8] %data, [4096 x i8]* %buffer static const unsigned MaxParallelChains = 64; +// True if the Value passed requires ABI mangling as it is a parameter to a +// function or a return value from a function which is not an intrinsic. +static bool isABIRegCopy(const Value * V) { + const bool IsRetInst = V && isa<ReturnInst>(V); + const bool IsCallInst = V && isa<CallInst>(V); + const bool IsInLineAsm = + IsCallInst && static_cast<const CallInst *>(V)->isInlineAsm(); + const bool IsIndirectFunctionCall = + IsCallInst && !IsInLineAsm && + !static_cast<const CallInst *>(V)->getCalledFunction(); + // It is possible that the call instruction is an inline asm statement or an + // indirect function call in which case the return value of + // getCalledFunction() would be nullptr. + const bool IsInstrinsicCall = + IsCallInst && !IsInLineAsm && !IsIndirectFunctionCall && + static_cast<const CallInst *>(V)->getCalledFunction()->getIntrinsicID() != + Intrinsic::not_intrinsic; + + return IsRetInst || (IsCallInst && (!IsInLineAsm && !IsInstrinsicCall)); +} + static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, @@ -1026,13 +1047,9 @@ SDValue SelectionDAGBuilder::getCopyFromRegs(const Val if (It != FuncInfo.ValueMap.end()) { unsigned InReg = It->second; - bool IsABIRegCopy = - V && ((isa<CallInst>(V) && - !(static_cast<const CallInst *>(V))->isInlineAsm()) || - isa<ReturnInst>(V)); RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), - DAG.getDataLayout(), InReg, Ty, IsABIRegCopy); + DAG.getDataLayout(), InReg, Ty, isABIRegCopy(V)); SDValue Chain = DAG.getEntryNode(); Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V); @@ -1221,13 +1238,9 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value // If this is an instruction which fast-isel has deferred, select it now. if (const Instruction *Inst = dyn_cast<Instruction>(V)) { unsigned InReg = FuncInfo.InitializeRegForValue(Inst); - bool IsABIRegCopy = - V && ((isa<CallInst>(V) && - !(static_cast<const CallInst *>(V))->isInlineAsm()) || - isa<ReturnInst>(V)); RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg, - Inst->getType(), IsABIRegCopy); + Inst->getType(), isABIRegCopy(V)); SDValue Chain = DAG.getEntryNode(); return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V); } @@ -8281,13 +8294,9 @@ SelectionDAGBuilder::CopyValueToVirtualRegister(const const TargetLowering &TLI = DAG.getTargetLoweringInfo(); // If this is an InlineAsm we have to match the registers required, not the // notional registers required by the type. - bool IsABIRegCopy = - V && ((isa<CallInst>(V) && - !(static_cast<const CallInst *>(V))->isInlineAsm()) || - isa<ReturnInst>(V)); RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg, - V->getType(), IsABIRegCopy); + V->getType(), isABIRegCopy(V)); SDValue Chain = DAG.getEntryNode(); ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) == Modified: vendor/llvm/dist/lib/CodeGen/StackColoring.cpp ============================================================================== --- vendor/llvm/dist/lib/CodeGen/StackColoring.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/CodeGen/StackColoring.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -37,6 +37,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/SlotIndexes.h" #include "llvm/CodeGen/StackProtector.h" #include "llvm/CodeGen/WinEHFuncInfo.h" @@ -889,6 +890,10 @@ void StackColoring::remapInstructions(DenseMap<int, in // Keep a list of *allocas* which need to be remapped. DenseMap<const AllocaInst*, const AllocaInst*> Allocas; + + // Keep a list of allocas which has been affected by the remap. + SmallPtrSet<const AllocaInst*, 32> MergedAllocas; + for (const std::pair<int, int> &SI : SlotRemap) { const AllocaInst *From = MFI->getObjectAllocation(SI.first); const AllocaInst *To = MFI->getObjectAllocation(SI.second); @@ -908,6 +913,10 @@ void StackColoring::remapInstructions(DenseMap<int, in Inst = Cast; } + // We keep both slots to maintain AliasAnalysis metadata later. + MergedAllocas.insert(From); + MergedAllocas.insert(To); + // Allow the stack protector to adjust its value map to account for the // upcoming replacement. SP->adjustForColoring(From, To); @@ -939,13 +948,6 @@ void StackColoring::remapInstructions(DenseMap<int, in // Update the MachineMemOperand to use the new alloca. for (MachineMemOperand *MMO : I.memoperands()) { - // FIXME: In order to enable the use of TBAA when using AA in CodeGen, - // we'll also need to update the TBAA nodes in MMOs with values - // derived from the merged allocas. When doing this, we'll need to use - // the same variant of GetUnderlyingObjects that is used by the - // instruction scheduler (that can look through ptrtoint/inttoptr - // pairs). - // We've replaced IR-level uses of the remapped allocas, so we only // need to replace direct uses here. const AllocaInst *AI = dyn_cast_or_null<AllocaInst>(MMO->getValue()); @@ -997,6 +999,48 @@ void StackColoring::remapInstructions(DenseMap<int, in MO.setIndex(ToSlot); FixedInstr++; } + + // We adjust AliasAnalysis information for merged stack slots. + MachineSDNode::mmo_iterator NewMemOps = + MF->allocateMemRefsArray(I.getNumMemOperands()); + unsigned MemOpIdx = 0; + bool ReplaceMemOps = false; + for (MachineMemOperand *MMO : I.memoperands()) { + // If this memory location can be a slot remapped here, + // we remove AA information. + bool MayHaveConflictingAAMD = false; + if (MMO->getAAInfo()) { + if (const Value *MMOV = MMO->getValue()) { + SmallVector<Value *, 4> Objs; + getUnderlyingObjectsForCodeGen(MMOV, Objs, MF->getDataLayout()); + + if (Objs.empty()) + MayHaveConflictingAAMD = true; + else + for (Value *V : Objs) { + // If this memory location comes from a known stack slot + // that is not remapped, we continue checking. + // Otherwise, we need to invalidate AA infomation. + const AllocaInst *AI = dyn_cast_or_null<AllocaInst>(V); + if (AI && MergedAllocas.count(AI)) { + MayHaveConflictingAAMD = true; + break; + } + } + } + } + if (MayHaveConflictingAAMD) { + NewMemOps[MemOpIdx++] = MF->getMachineMemOperand(MMO, AAMDNodes()); + ReplaceMemOps = true; + } + else + NewMemOps[MemOpIdx++] = MMO; + } + + // If any memory operand is updated, set memory references of + // this instruction. + if (ReplaceMemOps) + I.setMemRefs(std::make_pair(NewMemOps, I.getNumMemOperands())); } // Update the location of C++ catch objects for the MSVC personality routine. Modified: vendor/llvm/dist/lib/IR/ConstantFold.cpp ============================================================================== --- vendor/llvm/dist/lib/IR/ConstantFold.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/IR/ConstantFold.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -2097,15 +2097,19 @@ Constant *llvm::ConstantFoldGetElementPtr(Type *Pointe // Subsequent evaluation would get confused and produce erroneous results. // // The following prohibits such a GEP from being formed by checking to see - // if the index is in-range with respect to an array or vector. + // if the index is in-range with respect to an array. + // TODO: This code may be extended to handle vectors as well. bool PerformFold = false; if (Idx0->isNullValue()) PerformFold = true; else if (LastI.isSequential()) if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx0)) - PerformFold = - !LastI.isBoundedSequential() || - isIndexInRangeOfArrayType(LastI.getSequentialNumElements(), CI); + PerformFold = (!LastI.isBoundedSequential() || + isIndexInRangeOfArrayType( + LastI.getSequentialNumElements(), CI)) && + !CE->getOperand(CE->getNumOperands() - 1) + ->getType() + ->isVectorTy(); if (PerformFold) { SmallVector<Value*, 16> NewIndices; Modified: vendor/llvm/dist/lib/Object/COFFImportFile.cpp ============================================================================== --- vendor/llvm/dist/lib/Object/COFFImportFile.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/Object/COFFImportFile.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -542,15 +542,12 @@ NewArchiveMember ObjectFactory::createWeakExternal(Str SymbolTable[2].Name.Offset.Offset = sizeof(uint32_t); //__imp_ String Table - if (Imp) { - SymbolTable[3].Name.Offset.Offset = sizeof(uint32_t) + Sym.size() + 7; - writeStringTable(Buffer, {std::string("__imp_").append(Sym), - std::string("__imp_").append(Weak)}); - } else { - SymbolTable[3].Name.Offset.Offset = sizeof(uint32_t) + Sym.size() + 1; - writeStringTable(Buffer, {Sym, Weak}); - } + StringRef Prefix = Imp ? "__imp_" : ""; + SymbolTable[3].Name.Offset.Offset = + sizeof(uint32_t) + Sym.size() + Prefix.size() + 1; append(Buffer, SymbolTable); + writeStringTable(Buffer, {(Prefix + Sym).str(), + (Prefix + Weak).str()}); // Copied here so we can still use writeStringTable char *Buf = Alloc.Allocate<char>(Buffer.size()); Modified: vendor/llvm/dist/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -946,6 +946,18 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock & case AArch64::CMP_SWAP_128: return expandCMP_SWAP_128(MBB, MBBI, NextMBBI); + case AArch64::AESMCrrTied: + case AArch64::AESIMCrrTied: { + MachineInstrBuilder MIB = + BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(Opcode == AArch64::AESMCrrTied ? AArch64::AESMCrr : + AArch64::AESIMCrr)) + .add(MI.getOperand(0)) + .add(MI.getOperand(1)); + transferImpOps(MI, MIB, MIB); + MI.eraseFromParent(); + return true; + } } return false; } Modified: vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -506,19 +506,23 @@ void AArch64FrameLowering::emitPrologue(MachineFunctio return; } - auto CSStackSize = AFI->getCalleeSavedStackSize(); + bool IsWin64 = + Subtarget.isCallingConvWin64(MF.getFunction()->getCallingConv()); + unsigned FixedObject = IsWin64 ? alignTo(AFI->getVarArgsGPRSize(), 16) : 0; + + auto PrologueSaveSize = AFI->getCalleeSavedStackSize() + FixedObject; // All of the remaining stack allocations are for locals. - AFI->setLocalStackSize(NumBytes - CSStackSize); + AFI->setLocalStackSize(NumBytes - PrologueSaveSize); bool CombineSPBump = shouldCombineCSRLocalStackBump(MF, NumBytes); if (CombineSPBump) { emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -NumBytes, TII, MachineInstr::FrameSetup); NumBytes = 0; - } else if (CSStackSize != 0) { + } else if (PrologueSaveSize != 0) { MBBI = convertCalleeSaveRestoreToSPPrePostIncDec(MBB, MBBI, DL, TII, - -CSStackSize); - NumBytes -= CSStackSize; + -PrologueSaveSize); + NumBytes -= PrologueSaveSize; } assert(NumBytes >= 0 && "Negative stack allocation size!?"); @@ -532,8 +536,9 @@ void AArch64FrameLowering::emitPrologue(MachineFunctio ++MBBI; } if (HasFP) { - // Only set up FP if we actually need to. Frame pointer is fp = sp - 16. - int FPOffset = CSStackSize - 16; + // Only set up FP if we actually need to. Frame pointer is fp = + // sp - fixedobject - 16. + int FPOffset = AFI->getCalleeSavedStackSize() - 16; if (CombineSPBump) FPOffset += AFI->getLocalStackSize(); @@ -672,8 +677,8 @@ void AArch64FrameLowering::emitPrologue(MachineFunctio if (HasFP) { // Define the current CFA rule to use the provided FP. unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true); - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::createDefCfa(nullptr, Reg, 2 * StackGrowth)); + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa( + nullptr, Reg, 2 * StackGrowth - FixedObject)); BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) .setMIFlags(MachineInstr::FrameSetup); @@ -759,12 +764,16 @@ void AArch64FrameLowering::emitEpilogue(MachineFunctio // AArch64TargetLowering::LowerCall figures out ArgumentPopSize and keeps // it as the 2nd argument of AArch64ISD::TC_RETURN. - auto CSStackSize = AFI->getCalleeSavedStackSize(); + bool IsWin64 = + Subtarget.isCallingConvWin64(MF.getFunction()->getCallingConv()); + unsigned FixedObject = IsWin64 ? alignTo(AFI->getVarArgsGPRSize(), 16) : 0; + + auto PrologueSaveSize = AFI->getCalleeSavedStackSize() + FixedObject; bool CombineSPBump = shouldCombineCSRLocalStackBump(MF, NumBytes); - if (!CombineSPBump && CSStackSize != 0) + if (!CombineSPBump && PrologueSaveSize != 0) convertCalleeSaveRestoreToSPPrePostIncDec( - MBB, std::prev(MBB.getFirstTerminator()), DL, TII, CSStackSize); + MBB, std::prev(MBB.getFirstTerminator()), DL, TII, PrologueSaveSize); // Move past the restores of the callee-saved registers. MachineBasicBlock::iterator LastPopI = MBB.getFirstTerminator(); @@ -786,7 +795,7 @@ void AArch64FrameLowering::emitEpilogue(MachineFunctio return; } - NumBytes -= CSStackSize; + NumBytes -= PrologueSaveSize; assert(NumBytes >= 0 && "Negative stack allocation size!?"); if (!hasFP(MF)) { @@ -796,7 +805,7 @@ void AArch64FrameLowering::emitEpilogue(MachineFunctio if (RedZone && ArgumentPopSize == 0) return; - bool NoCalleeSaveRestore = CSStackSize == 0; + bool NoCalleeSaveRestore = PrologueSaveSize == 0; int StackRestoreBytes = RedZone ? 0 : NumBytes; if (NoCalleeSaveRestore) StackRestoreBytes += ArgumentPopSize; @@ -815,7 +824,8 @@ void AArch64FrameLowering::emitEpilogue(MachineFunctio // be able to save any instructions. if (MFI.hasVarSizedObjects() || AFI->isStackRealigned()) emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::FP, - -CSStackSize + 16, TII, MachineInstr::FrameDestroy); + -AFI->getCalleeSavedStackSize() + 16, TII, + MachineInstr::FrameDestroy); else if (NumBytes) emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP, NumBytes, TII, MachineInstr::FrameDestroy); @@ -845,7 +855,11 @@ int AArch64FrameLowering::resolveFrameIndexReference(c const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( MF.getSubtarget().getRegisterInfo()); const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); - int FPOffset = MFI.getObjectOffset(FI) + 16; + const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>(); + bool IsWin64 = + Subtarget.isCallingConvWin64(MF.getFunction()->getCallingConv()); + unsigned FixedObject = IsWin64 ? alignTo(AFI->getVarArgsGPRSize(), 16) : 0; + int FPOffset = MFI.getObjectOffset(FI) + FixedObject + 16; int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize(); bool isFixed = MFI.isFixedObjectIndex(FI); @@ -955,12 +969,6 @@ static void computeCalleeSaveRegisterPairs( (Count & 1) == 0) && "Odd number of callee-saved regs to spill!"); int Offset = AFI->getCalleeSavedStackSize(); - - unsigned GPRSaveSize = AFI->getVarArgsGPRSize(); - const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>(); - bool IsWin64 = Subtarget.isCallingConvWin64(MF.getFunction()->getCallingConv()); - if (IsWin64) - Offset -= alignTo(GPRSaveSize, 16); for (unsigned i = 0; i < Count; ++i) { RegPairInfo RPI; Modified: vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -9586,8 +9586,8 @@ static bool performTBISimplification(SDValue Addr, SelectionDAG &DAG) { APInt DemandedMask = APInt::getLowBitsSet(64, 56); KnownBits Known; - TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), - DCI.isBeforeLegalizeOps()); + TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), + !DCI.isBeforeLegalizeOps()); const TargetLowering &TLI = DAG.getTargetLoweringInfo(); if (TLI.SimplifyDemandedBits(Addr, DemandedMask, Known, TLO)) { DCI.CommitTargetLoweringOpt(TLO); Modified: vendor/llvm/dist/lib/Target/AArch64/AArch64InstrInfo.td ============================================================================== --- vendor/llvm/dist/lib/Target/AArch64/AArch64InstrInfo.td Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/Target/AArch64/AArch64InstrInfo.td Tue Aug 8 16:52:53 2017 (r322259) @@ -37,6 +37,9 @@ def HasFullFP16 : Predicate<"Subtarget->hasFullFP AssemblerPredicate<"FeatureFullFP16", "fullfp16">; def HasSPE : Predicate<"Subtarget->hasSPE()">, AssemblerPredicate<"FeatureSPE", "spe">; +def HasFuseAES : Predicate<"Subtarget->hasFuseAES()">, + AssemblerPredicate<"FeatureFuseAES", + "fuse-aes">; def HasSVE : Predicate<"Subtarget->hasSVE()">, AssemblerPredicate<"FeatureSVE", "sve">; @@ -5303,6 +5306,31 @@ def AESErr : AESTiedInst<0b0100, "aese", int_aarch def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>; def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>; def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>; + +// Pseudo instructions for AESMCrr/AESIMCrr with a register constraint required +// for AES fusion on some CPUs. +let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in { +def AESMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">, + Sched<[WriteV]>; +def AESIMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">, + Sched<[WriteV]>; +} + +// Only use constrained versions of AES(I)MC instructions if they are paired with +// AESE/AESD. +def : Pat<(v16i8 (int_aarch64_crypto_aesmc + (v16i8 (int_aarch64_crypto_aese (v16i8 V128:$src1), + (v16i8 V128:$src2))))), + (v16i8 (AESMCrrTied (v16i8 (AESErr (v16i8 V128:$src1), + (v16i8 V128:$src2)))))>, + Requires<[HasFuseAES]>; + +def : Pat<(v16i8 (int_aarch64_crypto_aesimc + (v16i8 (int_aarch64_crypto_aesd (v16i8 V128:$src1), + (v16i8 V128:$src2))))), + (v16i8 (AESIMCrrTied (v16i8 (AESDrr (v16i8 V128:$src1), + (v16i8 V128:$src2)))))>, + Requires<[HasFuseAES]>; def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>; def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>; Modified: vendor/llvm/dist/lib/Target/AArch64/AArch64MacroFusion.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/AArch64/AArch64MacroFusion.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/Target/AArch64/AArch64MacroFusion.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -118,11 +118,13 @@ static bool shouldScheduleAdjacent(const TargetInstrIn // Fuse AES crypto operations. switch(SecondOpcode) { // AES encode. - case AArch64::AESMCrr : + case AArch64::AESMCrr: + case AArch64::AESMCrrTied: return FirstOpcode == AArch64::AESErr || FirstOpcode == AArch64::INSTRUCTION_LIST_END; // AES decode. case AArch64::AESIMCrr: + case AArch64::AESIMCrrTied: return FirstOpcode == AArch64::AESDrr || FirstOpcode == AArch64::INSTRUCTION_LIST_END; } Modified: vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp ============================================================================== --- vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -3984,6 +3984,13 @@ bool MatchingStackOffset(SDValue Arg, unsigned Offset, if (Offset != MFI.getObjectOffset(FI)) return false; + // If this is not byval, check that the argument stack object is immutable. + // inalloca and argument copy elision can create mutable argument stack + // objects. Byval objects can be mutated, but a byval call intends to pass the + // mutated memory. + if (!Flags.isByVal() && !MFI.isImmutableObjectIndex(FI)) + return false; + if (VA.getLocVT().getSizeInBits() > Arg.getValueSizeInBits()) { // If the argument location is wider than the argument type, check that any // extension flags match. @@ -30605,8 +30612,8 @@ static SDValue combineSelect(SDNode *N, SelectionDAG & assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); APInt DemandedMask(APInt::getSignMask(BitWidth)); KnownBits Known; - TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), - DCI.isBeforeLegalizeOps()); + TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), + !DCI.isBeforeLegalizeOps()); if (TLI.ShrinkDemandedConstant(Cond, DemandedMask, TLO) || TLI.SimplifyDemandedBits(Cond, DemandedMask, Known, TLO)) { // If we changed the computation somewhere in the DAG, this change will Modified: vendor/llvm/dist/lib/Target/X86/X86InstrSSE.td ============================================================================== --- vendor/llvm/dist/lib/Target/X86/X86InstrSSE.td Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/Target/X86/X86InstrSSE.td Tue Aug 8 16:52:53 2017 (r322259) @@ -3697,8 +3697,7 @@ let SchedRW = [WriteNop] in { // Pause. This "instruction" is encoded as "rep; nop", so even though it // was introduced with SSE2, it's backward compatible. def PAUSE : I<0x90, RawFrm, (outs), (ins), - "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>, - OBXS, Requires<[HasSSE2]>; + "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>, OBXS; } let SchedRW = [WriteFence] in { Modified: vendor/llvm/dist/lib/Transforms/IPO/ArgumentPromotion.cpp ============================================================================== --- vendor/llvm/dist/lib/Transforms/IPO/ArgumentPromotion.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/Transforms/IPO/ArgumentPromotion.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -356,7 +356,7 @@ doPromotion(Function *F, SmallPtrSetImpl<Argument *> & // Just add all the struct element types. Type *AgTy = cast<PointerType>(I->getType())->getElementType(); Value *TheAlloca = new AllocaInst(AgTy, DL.getAllocaAddrSpace(), nullptr, - "", InsertPt); + I->getParamAlignment(), "", InsertPt); StructType *STy = cast<StructType>(AgTy); Value *Idxs[2] = {ConstantInt::get(Type::getInt32Ty(F->getContext()), 0), nullptr}; Modified: vendor/llvm/dist/lib/Transforms/Instrumentation/AddressSanitizer.cpp ============================================================================== --- vendor/llvm/dist/lib/Transforms/Instrumentation/AddressSanitizer.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/Transforms/Instrumentation/AddressSanitizer.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -756,7 +756,8 @@ struct FunctionStackPoisoner : public InstVisitor<Func bool runOnFunction() { if (!ClStack) return false; - if (ClRedzoneByvalArgs) copyArgsPassedByValToAllocas(); + if (ClRedzoneByvalArgs && Mapping.Offset != kDynamicShadowSentinel) + copyArgsPassedByValToAllocas(); // Collect alloca, ret, lifetime instructions etc. for (BasicBlock *BB : depth_first(&F.getEntryBlock())) visit(*BB); Modified: vendor/llvm/dist/lib/Transforms/Scalar/SCCP.cpp ============================================================================== --- vendor/llvm/dist/lib/Transforms/Scalar/SCCP.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/Transforms/Scalar/SCCP.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -1790,7 +1790,8 @@ static bool runIPSCCP(Module &M, const DataLayout &DL, // variables that do not have their 'addresses taken'. If they don't have // their addresses taken, we can propagate constants through them. for (GlobalVariable &G : M.globals()) - if (!G.isConstant() && G.hasLocalLinkage() && !AddressIsTaken(&G)) + if (!G.isConstant() && G.hasLocalLinkage() && + G.hasDefinitiveInitializer() && !AddressIsTaken(&G)) Solver.TrackValueOfGlobalVariable(&G); // Solve for constants. Modified: vendor/llvm/dist/lib/Transforms/Utils/CloneModule.cpp ============================================================================== --- vendor/llvm/dist/lib/Transforms/Utils/CloneModule.cpp Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/lib/Transforms/Utils/CloneModule.cpp Tue Aug 8 16:52:53 2017 (r322259) @@ -132,7 +132,8 @@ std::unique_ptr<Module> llvm::CloneModule( SmallVector<std::pair<unsigned, MDNode *>, 1> MDs; I->getAllMetadata(MDs); for (auto MD : MDs) - GV->addMetadata(MD.first, *MapMetadata(MD.second, VMap)); + GV->addMetadata(MD.first, + *MapMetadata(MD.second, VMap, RF_MoveDistinctMDs)); copyComdat(GV, &*I); } Modified: vendor/llvm/dist/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll ============================================================================== --- vendor/llvm/dist/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll Tue Aug 8 16:52:53 2017 (r322259) @@ -2,14 +2,14 @@ define win64cc void @pass_va(i32 %count, ...) nounwind { entry: -; CHECK: sub sp, sp, #80 +; CHECK: str x30, [sp, #-80]! ; CHECK: add x8, sp, #24 ; CHECK: add x0, sp, #24 ; CHECK: stp x6, x7, [sp, #64] ; CHECK: stp x4, x5, [sp, #48] ; CHECK: stp x2, x3, [sp, #32] ; CHECK: str x1, [sp, #24] -; CHECK: stp x30, x8, [sp] +; CHECK: str x8, [sp, #8] ; CHECK: bl other_func ; CHECK: ldr x30, [sp], #80 ; CHECK: ret Modified: vendor/llvm/dist/test/CodeGen/AArch64/misched-fusion-aes.ll ============================================================================== --- vendor/llvm/dist/test/CodeGen/AArch64/misched-fusion-aes.ll Tue Aug 8 16:14:31 2017 (r322258) +++ vendor/llvm/dist/test/CodeGen/AArch64/misched-fusion-aes.ll Tue Aug 8 16:52:53 2017 (r322259) @@ -1,10 +1,10 @@ -; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=+fuse-aes,+crypto | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS -; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=generic -mattr=+crypto | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS -; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a53 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS -; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS -; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS -; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS -; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKM1 +; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=+fuse-aes,+crypto | FileCheck %s +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=generic -mattr=+crypto | FileCheck %s +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a53 | FileCheck %s +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 | FileCheck %s +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m1 | FileCheck %s declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %d, <16 x i8> %k) declare <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %d) @@ -76,41 +76,23 @@ define void @aesea(<16 x i8>* %a0, <16 x i8>* %b0, <16 ret void ; CHECK-LABEL: aesea: -; CHECKFUSEALLPAIRS: aese [[VA:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VA]] -; CHECKFUSEALLPAIRS: aese [[VB:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VB]] -; CHECKFUSEALLPAIRS: aese [[VC:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VC]] -; CHECKFUSEALLPAIRS: aese [[VD:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VD]] -; CHECKFUSEALLPAIRS: aese [[VE:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VE]] -; CHECKFUSEALLPAIRS: aese [[VF:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VF]] -; CHECKFUSEALLPAIRS: aese [[VG:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VG]] -; CHECKFUSEALLPAIRS: aese [[VH:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VH]] -; CHECKFUSEALLPAIRS-NOT: aesmc - -; CHECKM1: aese [[VA:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VA]] -; CHECKM1: aese [[VH:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1: aese [[VB:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VB]] -; CHECKM1: aese {{v[0-7].16b}}, {{v[0-7].16b}} -; CHECKM1: aese [[VC:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VC]] -; CHECKM1: aese [[VD:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VD]] -; CHECKM1: aesmc {{v[0-7].16b}}, [[VH]] -; CHECKM1: aese [[VE:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VE]] -; CHECKM1: aese [[VF:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VF]] -; CHECKM1: aese [[VG:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VG]] +; CHECK: aese [[VA:v[0-7].16b]], {{v[0-7].16b}} +; CHECK-NEXT: aesmc [[VA]], [[VA]] +; CHECK: aese [[VB:v[0-7].16b]], {{v[0-7].16b}} +; CHECK-NEXT: aesmc [[VB]], [[VB]] +; CHECK: aese [[VC:v[0-7].16b]], {{v[0-7].16b}} +; CHECK-NEXT: aesmc [[VC]], [[VC]] +; CHECK: aese [[VD:v[0-7].16b]], {{v[0-7].16b}} +; CHECK-NEXT: aesmc [[VD]], [[VD]] +; CHECK: aese [[VE:v[0-7].16b]], {{v[0-7].16b}} +; CHECK-NEXT: aesmc [[VE]], [[VE]] +; CHECK: aese [[VF:v[0-7].16b]], {{v[0-7].16b}} +; CHECK-NEXT: aesmc [[VF]], [[VF]] +; CHECK: aese [[VG:v[0-7].16b]], {{v[0-7].16b}} +; CHECK-NEXT: aesmc [[VG]], [[VG]] +; CHECK: aese [[VH:v[0-7].16b]], {{v[0-7].16b}} +; CHECK-NEXT: aesmc [[VH]], [[VH]] +; CHECK-NOT: aesmc } define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d, <16 x i8> %e) { @@ -178,41 +160,23 @@ define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 ret void ; CHECK-LABEL: aesda: -; CHECKFUSEALLPAIRS: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VA]] -; CHECKFUSEALLPAIRS: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VB]] -; CHECKFUSEALLPAIRS: aesd [[VC:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VC]] -; CHECKFUSEALLPAIRS: aesd [[VD:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VD]] -; CHECKFUSEALLPAIRS: aesd [[VE:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VE]] -; CHECKFUSEALLPAIRS: aesd [[VF:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VF]] -; CHECKFUSEALLPAIRS: aesd [[VG:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VG]] -; CHECKFUSEALLPAIRS: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}} -; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VH]] -; CHECKFUSEALLPAIRS-NOT: aesimc - -; CHECKM1: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VA]] -; CHECKM1: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VB]] -; CHECKM1: aesd {{v[0-7].16b}}, {{v[0-7].16b}} -; CHECKM1: aesd [[VC:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VC]] -; CHECKM1: aesd [[VD:v[0-7].16b]], {{v[0-7].16b}} -; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VD]] -; CHECKM1: aesimc {{v[0-7].16b}}, [[VH]] -; CHECKM1: aesd [[VE:v[0-7].16b]], {{v[0-7].16b}} *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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