Date: Mon, 18 Feb 2008 00:19:30 +0800 From: Erich Dollansky <oceanare@pacific.net.sg> To: Andriy Gapon <avg@icyb.net.ua> Cc: freebsd-hackers@freebsd.org Subject: Re: multiple interrupts between cli and sti Message-ID: <47B85E92.9010206@pacific.net.sg> In-Reply-To: <47B855C0.4010703@icyb.net.ua> References: <47B855C0.4010703@icyb.net.ua>
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Hi, Andriy Gapon wrote: I cannot tell you if this is still the same for modern designs. > ... -> iret -> interrupted again This was the behaviour earlier. > > Is this a deterministic behavior ? Or some timings are at play? The PIC should never release the Interrupt signal to the CPU as long as a single interrupt is not serviced. But the 8259 can be programmed to trigger via level or slope. So, this behaviour is only seen when level triggering is used. As I said at the bginning, I do not know how current designs handle it. Erich
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