Date: Wed, 16 Jun 2004 12:46:30 +0200 From: Alexander Leidinger <Alexander@Leidinger.net> To: Bruce M Simpson <bms@spc.org> Subject: Re: How to determine the L2 cache size on non-AMD CPUs (automatic page queue color tuning)? Message-ID: <20040616124630.34c80d7a@Magellan.Leidinger.net> In-Reply-To: <20040616101102.GQ32244@empiric.dek.spc.org> References: <20040616112758.46677e25@Magellan.Leidinger.net> <40D016F2.2080904@gneto.com> <20040616101102.GQ32244@empiric.dek.spc.org>
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On Wed, 16 Jun 2004 11:11:02 +0100 Bruce M Simpson <bms@spc.org> wrote: > On Wed, Jun 16, 2004 at 11:46:26AM +0200, Martin Nilsson wrote: > > The more expensive intel processors also have L3 caches of 1-4MB. > > Since intels processors are built with inclusive caches (data in L2 > > cache is also present in L3) shouldn't the value used be that of the > > largest cache be it L2 or L3? > > > > How much effct on performance does a wrong cache size value have? > > Gag. I posted something on this whole subject last *year*, and still > haven't gotten round to code. I found it: http://unix.derkeiler.com/Mailing-Lists/FreeBSD/hackers/2003-06/0462.html Bye, Alexander. -- I'm available to get hired (preferred in .lu). http://www.Leidinger.net Alexander @ Leidinger.net GPG fingerprint = C518 BC70 E67F 143F BE91 3365 79E2 9C60 B006 3FE7
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