Date: Sat, 13 Jan 1996 00:39:21 +0100 From: se@zpr.uni-koeln.de (Stefan Esser) To: Bruce Evans <bde@zeta.org.au> Cc: freebsd-hackers@freebsd.org Subject: Re: PnP problem... Message-ID: <199601140041.QAA00417@freefall.freebsd.org> In-Reply-To: Bruce Evans <bde@zeta.org.au> "Re: PnP problem..." (Jan 13, 1:42)
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On Jan 13, 1:42, Bruce Evans wrote: } Subject: Re: PnP problem... } >} Hmm. How do the ISA probes avoid rediscovering PCI/EISA devices? What } } >Well, that's easy, actually :) } } >The ISA driver probe will find a conflict with } >ressources reserved by the earlier PCI probe. } } >This makes the PCI probe win :) } } I'd like to avoid ordering dependencies like that. Yes, of course ! I assumed that the probe and attach phases are split (as proposed by Justin Gibbs and others). This makes PCI win because the probe phase will show the conflict and the attach phase will resolve the conflict with preference to the more intelligent bus (PCI,EISA,PnP). } >And that is the right thing to do, since it is } >most likely, that the PCI driver will be able } >to correctly setup interrupts, for example, or } >it may choose to use memory mapped I/O instead } >of the traditional port I/O of the ISA variant. } } We were thinking about doing the ISA probe first since the ISA } devices can't be moved and the other drivers might need to know } where they are in order to keep out of their way. Is this actually } a consideration for PCI? PCI devices get their port and memory ranges assigned by the PCI BIOS at POST time (or are left alone, if the BIOS considers them of no value as boot device and leaves the init to the actual OS code). If the PCI chip emulates some ISA device, then there will be a mapping to the official standard address in the 640K++ ISA device window, if that range has not been assigned to some other PCI device before. (Don't know, how intelligent the test is. If the inactive bus returns a known logical state, then a non-destructive test for ANY card in that range was possible, I suppose.) Devices that are not mapped into some ISA range are generally put on some address outside the supported RAM range (i.e. >256MB, often >3GB). Port addresses are often assigned in the 0xf000 range, but 0x7000 seems to be preferred by Compaq. } >} 0-0x3ff :-). I think ISA probes will have to be just as invasive as } } >Well, yes. You never know how many address bits } >an ISA device actually decodes ... } } Oops, 0-0xffff :-) Well, I guess you can't rely on an ISA device checking more than 10 address lines. And this might make it appeas some 64 times in the 64K port address space :( I'm not sure how a PCI BIOS deals with that situation. But since PCI devices actively acknowledge each access, it is easy to have the PCI to ISA bridge apply the addresses for an ISA access, and not assert any ISA control lines, if some PCI card responds within some number of PCI bus clocks (the DEVSEL# line will be activated, but I do not remember the maximum time allowed to apply that signal). (I have no actual PCI chip set data book here but I can try to find that information at home.) This allows for substractive decoding, i.e. only those accesses that do not address any PCI device will become effective on the ISA bus, mapping a PCI chip over such an address would hide the ISA ports ... } >(This might be a prameter to the confict check: } >let it know, how many address bits the adapter } >is known to decode (e.g. 10) and make all tests } >modulo 2^N). } } Do we want to handle things like the sio3 vs S3 card conflict } automatically? Presumably, for sio3, sio would return iobase = 0x2e8, } length = 8, decoding = 10 bits (worst case must be assumed unless } overridden). syscons would have a harder time deciding whether } there is an S3 using 0x2e8-0x2ef. Well, as said above, if I'm not totally wrong, then the PCI access to some address above 0x3ff (guess you were right it is twelve bits, not ten) will not be seen on the ISA bus at all. Guess the parameters you propose (base, size and decoding) will be sufficient, and should in fact default to safe values for ISA. But I've read that some PCI chips are guilty of not fully decoding the address lines, too, so specifying a decoding value should be possible for them, too. Just that the default could be 16 bits ... A few people in the FreeBSD lists seem to have deeper insight into BIOS programming. Perhaps somebody can give some insight into PCI BIOS coding practice ? Regards, STefan -- Stefan Esser, Zentrum fuer Paralleles Rechnen Tel: +49 221 4706021 Universitaet zu Koeln, Weyertal 80, 50931 Koeln FAX: +49 221 4705160 ============================================================================== http://www.zpr.uni-koeln.de/~se <se@ZPR.Uni-Koeln.DE>
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