Date: Thu, 21 Feb 2008 23:17:06 GMT From: "Randall R. Stewart" <rrs@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 135920 for review Message-ID: <200802212317.m1LNH62I002889@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=135920 Change 135920 by rrs@rrs-mips2-jnpr on 2008/02/21 23:16:32 cleanup style..and an adjustment to clock rate setting. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/octeon_machdep.c#15 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/octeon_machdep.c#15 (text+ko) ==== @@ -197,7 +197,7 @@ -static __inline u_int32_t +static __inline u_int32_t mips_rd_ebase(void) { int v0; @@ -208,7 +208,7 @@ return (v0); } -static __inline void +static __inline void mips_wr_ebase(u_int32_t a0) { __asm __volatile("mtc0 %[a0], $15, 1 ;" @@ -223,7 +223,7 @@ * Perform a board-level soft-reset. * Note that this is not emulated by gxemul. */ -void +void octeon_reset(void) { void (*reset_func) (void)= (void (*) (void))0x1fc00000; @@ -232,7 +232,7 @@ } -static inline uint32_t +static inline uint32_t octeon_disable_interrupts(void) { uint32_t status_bits; @@ -243,14 +243,14 @@ } -static inline void +static inline void octeon_set_interrupts(uint32_t status_bits) { mips_wr_status(status_bits); } -void +void octeon_led_write_char(int char_position, char val) { uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); @@ -263,7 +263,7 @@ oct_write8_x8(ptr, val); } -void +void octeon_led_write_char0(char val) { uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); @@ -274,7 +274,7 @@ oct_write8_x8(ptr, val); } -void +void octeon_led_write_hexchar(int char_position, char hexval) { uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); @@ -296,7 +296,7 @@ oct_write8_x8(ptr, char2); } -void +void octeon_led_write_string(const char *str) { uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); @@ -319,7 +319,7 @@ int prog_count = 0; -void +void octeon_led_run_wheel(void) { if (!octeon_board_real()) @@ -350,7 +350,7 @@ * Put out a single byte off of uart port. */ -void +void octeon_uart_write_byte(int uart_index, uint8_t ch) { uint64_t val, val2; @@ -368,7 +368,10 @@ } /* Write the byte */ - /*oct_write8(OCTEON_MIO_UART0_THR + (uart_index * 0x400), (uint64_t) ch); */ + /* + * oct_write8(OCTEON_MIO_UART0_THR + (uart_index * 0x400), + * (uint64_t) ch); + */ oct_write64(OCTEON_MIO_UART0_THR + (uart_index * 0x400), (uint64_t) ch); /* Force Flush the IOBus */ @@ -376,7 +379,7 @@ } -void +void octeon_uart_write_byte0(uint8_t ch) { uint64_t val, val2; @@ -391,7 +394,7 @@ } /* Write the byte */ - /*oct_write8(OCTEON_MIO_UART0_THR, (uint64_t) ch); */ + /* oct_write8(OCTEON_MIO_UART0_THR, (uint64_t) ch); */ oct_write64(OCTEON_MIO_UART0_THR, (uint64_t) ch); /* Force Flush the IOBus */ @@ -402,7 +405,7 @@ * octeon_uart_write_string * */ -void +void octeon_uart_write_string(int uart_index, const char *str) { /* Just loop writing one byte at a time */ @@ -418,7 +421,7 @@ static char wstr[30]; -void +void octeon_led_write_hex(uint32_t wl) { char nbuf[80]; @@ -428,14 +431,14 @@ } -void +void octeon_uart_write_hex2(uint32_t wl, uint32_t wh) { sprintf(wstr, "0x%X-0x%X ", wh, wl); octeon_uart_write_string(0, wstr); } -void +void octeon_uart_write_hex(uint32_t wl) { sprintf(wstr, " 0x%X ", wl); @@ -445,7 +448,7 @@ /* * octeon_wait_uart_flush */ -void +void octeon_wait_uart_flush(int uart_index, uint8_t ch) { uint64_t val; @@ -474,18 +477,18 @@ * Does nothing. * Used to mark the point for simulator to begin tracing */ -void +void octeon_debug_symbol(void) { } -void +void octeon_ciu_stop_gtimer(int timer) { oct_write64(OCTEON_CIU_GENTIMER_ADDR(timer), 0ll); } -void +void octeon_ciu_start_gtimer(int timer, u_int one_shot, uint64_t time_cycles) { octeon_ciu_gentimer gentimer; @@ -501,7 +504,7 @@ * * Shutdown all CIU to IP2, IP3 mappings */ -void +void octeon_ciu_reset(void) { @@ -525,7 +528,7 @@ * * Disable interrupts in the CPU controller */ -void +void mips_disable_interrupt_controls(void) { /* @@ -539,7 +542,7 @@ /* * ciu_get_intr_sum_reg_addr */ -static uint64_t +static uint64_t ciu_get_intr_sum_reg_addr(int core_num, int intx, int enx) { uint64_t ciu_intr_sum_reg_addr; @@ -561,7 +564,7 @@ /* * ciu_get_intr_en_reg_addr */ -static uint64_t +static uint64_t ciu_get_intr_en_reg_addr(int core_num, int intx, int enx) { uint64_t ciu_intr_reg_addr; @@ -595,7 +598,7 @@ * 238 ---int1,en1 ip3 * */ -uint64_t +uint64_t ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip) { uint64_t ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR; @@ -628,7 +631,8 @@ /* * ciu_get_int_summary */ -uint64_t ciu_get_int_summary(int core_num, int intx, int enx) +uint64_t +ciu_get_int_summary(int core_num, int intx, int enx) { uint64_t ciu_intr_sum_reg_addr; @@ -644,7 +648,7 @@ /* * ciu_clear_int_summary */ -void +void ciu_clear_int_summary(int core_num, int intx, int enx, uint64_t write_bits) { uint32_t cpu_status_bits; @@ -652,7 +656,8 @@ #ifdef DEBUG_CIU_SUM - uint64_t ciu_intr_sum_bits; + uint64_t ciu_intr_sum_bits; + #endif @@ -688,7 +693,7 @@ /* * ciu_disable_intr */ -void +void ciu_disable_intr(int core_num, int intx, int enx) { uint32_t cpu_status_bits; @@ -710,7 +715,7 @@ } void ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip); -void +void ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip) { @@ -740,7 +745,7 @@ /* * ciu_enable_interrupts */ -void +void ciu_enable_interrupts(int core_num, int intx, int enx, uint64_t set_these_interrupt_bits, int ciu_ip) { @@ -752,9 +757,8 @@ if (core_num == CIU_THIS_CORE) { core_num = octeon_get_core_num(); } - #ifdef DEBUG_CIU_EN - printf(" CIU: core %u enabling Intx %u Enx %u IP %d Bits: 0x%llX\n", + printf(" CIU: core %u enabling Intx %u Enx %u IP %d Bits: 0x%llX\n", core_num, intx, enx, ciu_ip, set_these_interrupt_bits); #endif @@ -932,8 +936,8 @@ uint32_t octeon_cpu_clock; uint64_t octeon_dram = 0; -uint32_t octeon_bd_ver = 0, octeon_cvmx_bd_ver = 0, octeon_board_rev_major, - octeon_board_rev_minor, octeon_board_type; +uint32_t octeon_bd_ver = 0, octeon_cvmx_bd_ver = 0, octeon_board_rev_major, octeon_board_rev_minor, + octeon_board_type; uint8_t octeon_mac_addr[6] = {0}; int octeon_core_mask, octeon_mac_addr_count; int octeon_chip_rev_major = 0, octeon_chip_rev_minor = 0, octeon_chip_type = 0; @@ -954,7 +958,7 @@ #define OCTEON_DRAM_MAX 3000 -int +int octeon_board_real(void) { if ((octeon_board_type == OCTEON_BOARD_TYPE_NONE) || @@ -965,7 +969,7 @@ return 1; } -static void +static void octeon_process_app_desc_ver_unknown(void) { printf(" Unknown Boot-Descriptor: Using Defaults\n"); @@ -987,7 +991,7 @@ octeon_mac_addr_count = 1; } -static int +static int octeon_process_app_desc_ver_6(void) { cvmx_desc_ptr = (cvmx_bootinfo_t *) ((long)app_desc_ptr->cvmx_desc_vaddr); @@ -1032,7 +1036,7 @@ return 0; } -static int +static int octeon_process_app_desc_ver_3_4_5(void) { @@ -1114,7 +1118,7 @@ #define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0) #define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET (1ull << 1) -int +int octeon_is_pci_host(void) { #if (CVMX_BOOTINFO_MIN_VER >= 2) @@ -1317,6 +1321,7 @@ __register_t a2 __unused, __register_t a3 __unused) { vm_offset_t kernend; + uint64_t platform_counter_freq; mips_platform_init(); @@ -1333,7 +1338,7 @@ printf(" Initialized memory: 0x%p to 0x%lX\n", &edata, ((long)&edata) + ((long)kernend - (long)(&edata))); mips_init(); - uint64_t platform_counter_freq = OCTEON_CLOCK_DEFAULT; + platform_counter_freq = (uint64_t) (octeon_get_clock_rate()); tick_init_params(platform_counter_freq, 0); }
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