Date: Sun, 11 Dec 2011 21:54:26 +0100 From: Stefan Bethke <stb@lassitu.de> To: Adrian Chadd <adrian@freebsd.org> Cc: freebsd-embedded@freebsd.org Subject: Re: TL-WR1043: switch Message-ID: <E2992227-7989-4278-8BA8-1ADDA0A58FDC@lassitu.de> In-Reply-To: <CAJ-Vmo=zn7K35Tk%2BkoHs8Kba9C9ypMCdJjSU=2O1TfwohV9GzQ@mail.gmail.com> References: <68ABED76-CB1F-405A-8036-EC254F7511FA@lassitu.de> <3B3DB17D-BF87-40EE-B1C1-445F178E8844@lassitu.de> <86030CEE-6839-4B96-ACDC-2BA9AC1E4AE4@lassitu.de> <2D625CC9-A0E3-47AA-A504-CE8FB2F90245@lassitu.de> <203BF1C8-D528-40C9-8611-9C7AC7E43BAB@lassitu.de> <3C0E9CA3-E130-4E9A-ABCC-1782E28999D1@lassitu.de> <CAJ-VmomWsGy9wMb0zA-WjTRP6Qh%2BO2u_Pe-rgkerFFpi04iKnw@mail.gmail.com> <6387ABA5-AC55-49DD-9058-E45CC0A3E0A0@lassitu.de> <CAJ-VmonM91s-kbbEqVDy9PvtH-gxLWYmusGiqzqCWMtfMdoo2A@mail.gmail.com> <EA0807C1-6FEE-4743-8DCA-1AC873664005@lassitu.de> <74E4AF57-3D22-415E-B913-176753B09B16@lassitu.de> <710E2C7A-E9AC-4103-8C61-0EDC4A3AF9DE@lassitu.de> <CAJ-Vmo=zn7K35Tk%2BkoHs8Kba9C9ypMCdJjSU=2O1TfwohV9GzQ@mail.gmail.com>
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Am 11.12.2011 um 21:28 schrieb Adrian Chadd:
> Hm, so - how does this expose the CPU facing port(s), if any?
>=20
> ray@ is trying to figure out how to expose the arge0/arge1 interface
> (as he's got at least one board where the switch PHY hangs off of
> arge1, not arge0) so things are probed/attached "right".
>=20
> That discussion may be worth having here. :)
The RTL8366 family of switches has a GMII interface to hook up an =
ethernet controller. MDC/MDIO are not connected to the ethernet =
controller, instead register access is through this I2C-like interface, =
which on the TL-WR1043ND is through two GPIOs.
The RTL8306SD (which is used for example in the Linksys WRT160NL) has =
two MII ports. One is always used to connect a CPU, while the second one =
can be configured to either communicate with the switch or with one =
specific PHY. I believe the WRT160NL uses the latter mode, using the =
first ethernet port of the CPU to talk to the switch ("LAN"), and the =
second one to the PHY ("WAN"). It exposes both the five PHYs via =
MDC/MDIO, as well as switch configuration. Unfortunately, the =
configuration registers are spread out over all the PHYs, so you can't =
cleanly isolate the PHYs from the switch portion. Since the switch has =
only one set of MDC/MDIO, both ethernet controllers share the same =
minibus (and both driver instances need to work on just the one =
instance). For arge1, using the appropriate phymask should be =
sufficient.
We already have PHY support for the similar RTL8305 in the tree =
(sys/dev/mii/rlswitch.c), which does configure the switch. I haven't =
looked at how it handles the multiple exposed PHYs.
BTW, would it make sense to put all this info up on a wiki page =
somewhere? I'm optimistic that we can flesh the code out in the next =
couple of weeks, but it would be sad to bury all the additional =
information just in the mailing list archives.
> Whats RTL8366RB_SGCR_EN_VLAN_4KTB do?
The switch also supports a mode where theres a configuration per VID, so =
it can support all possible VIDs (1-4094). I cna add the code, but I =
don't think it really adds that many real-world functionality.
Stefan
--=20
Stefan Bethke <stb@lassitu.de> Fon +49 151 14070811
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