Date: Thu, 17 Aug 1995 23:16:46 -0700 (PDT) From: "Rodney W. Grimes" <rgrimes@gndrsh.aac.dev.com> To: jmb@kryten.Atinc.COM (Jonathan M. Bresler) Cc: freebsd-hardware@freebsd.org Subject: Re: i82424ZX vs i82424TX cache dram controller Message-ID: <199508180616.XAA24364@gndrsh.aac.dev.com> In-Reply-To: <Pine.3.89.9508171006.H3048-0100000@kryten.atinc.com> from "Jonathan M. Bresler" at Aug 17, 95 10:56:34 am
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> > On Wed, 16 Aug 1995, Rodney W. Grimes wrote: > > > > ps. the asus sp3g uses: > > > chip0 <intel 82424ZX cache dram controller> on pci0:0 > > > chip1 <intel 82378IB pci-isa bridge> on pci0:2 > > > > You left out a bit of that string, and it is an important part: > > chip0 <Intel 82424ZX cache DRAM controller> rev 4 on pci0:0 > > ^^^^^ > > As far as I can assertain rev 0, 1 and 2 are Saturn I, 3 and 4 > > are Saturn II. Since Intel data books do not publish code names, > > it is very hard to figure these things out at times :-(. > > hmm...looking into pcisupport.c, i see that most printf()'s are > #ifdef'ed PROBE_VERBOSE. with PROBE_VERBOSE defined i get: > > pci0: scanning device 0..15, mechanism=2. > chip0 <intel 82424ZX cache dram controller> on pci0:0 > CPU: 486DX2 or 486DX4, bus=33MHz, CPU->Memory posting ON > Warning: NO DRAM parity! > Cache: 256KB writethrough, cache clocks=2-1-1-1 > DRAM: page mode code fetch, read and write, memory clocks=X-1-2-1 > CPU->PCI: posting ON, burst mode OFF > PCI->Memory: posting ON > [snip] > chip1 <intel 82378IB pci-isa bridge> on pci0:2 > [40] 41e23 [50] 0 [54] 4000000 > > > still no rev message--from looking at source that seems to be in > -current and 2.0.5R but not in 2.0R Oopss.. your running old code :-(... -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Reliable computers for FreeBSD
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