Date: Tue, 28 Jul 1998 12:59:30 -0600 (MDT) From: "Justin T. Gibbs" <gibbs@narnia.plutotech.com> To: Karl Denninger <karl@mcs.net> Cc: scsi@FreeBSD.ORG Subject: Re: New problem - Adaptec cards with REV E on the sequencer chipset Message-ID: <199807281859.MAA03528@narnia.plutotech.com> In-Reply-To: <19980728071337.07188@mcs.net> <Pine.BSF.3.96.980728093345.15349H-200000@hub.org> <19980728090821.09162@mcs.net>
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In article <19980728090821.09162@mcs.net> you wrote: > > Does anyone know what, specifically, this fixes and whether or not this > problem could cause any other symptoms in a non-fixed CAM kernel > (other than failures with REV E cards)? If you really must know... While cost reducing the aic7880 part, Adaptec added an 8 byte input latch on the PCI side. This latch is supposed to buffer writes into the internal 8 byte x 32 entry data FIFO in the chip. It just so happens that Intel, in it's infinite wisdom, decided to use a 28 byte cacheline size on some of it's chipsets. The new Adaptec part doesn't understand cachelines that are not a multiple of 8, so it performs a single memory read line to fetch anything within the 24->32 byte window. So, if we request 32 bytes, we wind up with only a partially filled input latch and the aic7880 doesn't perform the second memory read to fill in the last 4 bytes. Since the data is never fetched, we hang waiting for it to arrive. For SCSI data, this isn't a problem as the chip as the logic that determines the amount of data to retrieve avoids fetch sizes that can confuse the chip. There are ways to detect whether this condition will occur and and work around it, but it is simpler to simply change the size of the fetch. Right now I don't need the last 4 bytes of the SCB, but I had planned to use them soon. I'll cross that bridge when I get there I suppose. -- Justin To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-scsi" in the body of the message
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