Date: Thu, 31 Jan 2008 17:21:14 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 134554 for review Message-ID: <200801311721.m0VHLE2G077213@repoman.freebsd.org>
next in thread | raw e-mail | index | archive | help
http://perforce.freebsd.org/chv.cgi?CH=134554 Change 134554 by imp@imp_lighthouse on 2008/01/31 17:20:22 It is bad kharma to write the same address to multiple TLB entries. Use the KSEG3 addresses from mips2 since they are unique and invalid. Not sure how this code could have ever worked for real mips hardware... Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/tlb.S#5 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/tlb.S#5 (text+ko) ==== @@ -230,7 +230,7 @@ mtc0 zero, COP_0_STATUS_REG # Disable interrupts ITLBNOPFIX mfc0 t1, COP_0_TLB_WIRED - li v0, MIPS_KSEG0_START # invalid address + li v0, MIPS_KSEG3_START + 0x0fff0000 # invalid address _MFC0 t0, COP_0_TLB_HI # Save the PID _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid @@ -242,7 +242,10 @@ */ 1: mtc0 t1, COP_0_TLB_INDEX # Set the index register. + ITLBNOPFIX + _MTC0 t0, COP_0_TLB_HI # Restore the PID addu t1, t1, 1 # Increment index. + addu t0, t0, 8 * 1024 MIPS_CPU_NOP_DELAY tlbwi # Write the TLB entry. MIPS_CPU_NOP_DELAY
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200801311721.m0VHLE2G077213>