Date: Thu, 11 Dec 2003 22:28:53 +0100 From: "Joachim Strombergson" <watchman@ludd.luth.se> To: FreeBSD-gnats-submit@FreeBSD.org Subject: ports/60162: Update of Icarus Verilog to 2003-12-02 snapshot (this fixes the broken port) Message-ID: <1071178122@fetis.ninja.se> Resent-Message-ID: <200312112130.hBBLU4ew061417@freefall.freebsd.org>
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>Number: 60162 >Category: ports >Synopsis: Update of Icarus Verilog to 2003-12-02 snapshot (this fixes the broken port) >Confidential: no >Severity: non-critical >Priority: medium >Responsible: freebsd-ports-bugs >State: open >Quarter: >Keywords: >Date-Required: >Class: maintainer-update >Submitter-Id: current-users >Arrival-Date: Thu Dec 11 13:30:03 PST 2003 >Closed-Date: >Last-Modified: >Originator: Joachim Strombergson >Release: FreeBSD 5.1-CURRENT i386 >Organization: >Environment: System: FreeBSD fetis.ninja.se 5.1-CURRENT FreeBSD 5.1-CURRENT #0: Sat Nov 15 16:16:05 CET 2003 root@fetis.ninja.se:/usr/obj/usr/src/sys/ATHLON i386 >Description: The port of Icarus Verilog have been broken for a while with a problem upstream. I have been in contact with the author of Icarus Verilog who has now released a new development snapshot of the port. I have created patches that updates the port to the snapshot and have tested it on CURRENT. The problem seen with PLI_UINT64 have been fixed. Additionally the snapshot adds several nerw functions for FPGA development. NOTE: The patches and thereby the port have not been tested on STABLE. >How-To-Repeat: Apply the included patches. >Fix: --- distinfo.patch begins here --- --- distinfo Sat Nov 15 14:07:22 2003 +++ distinfo Thu Dec 11 21:06:19 2003 @@ -1 +1 @@ -MD5 (verilog-20031009.tar.gz) = d4d78212b4f7dde22555cdac5a52b468 +MD5 (verilog-20031202.tar.gz) = 14401d3da60ee3da3043523684fbb442 --- distinfo.patch ends here --- --- Makefile.patch begins here --- --- Makefile Mon Nov 24 18:35:20 2003 +++ Makefile Thu Dec 11 21:03:58 2003 @@ -7,15 +7,13 @@ # PORTNAME= iverilog -PORTVERSION= 0.7.20031009 +PORTVERSION= 0.7.20031202 CATEGORIES= cad MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/ -DISTNAME= verilog-20031009 +DISTNAME= verilog-20031202 MAINTAINER= watchman@ludd.luth.se COMMENT= A Verilog simulation and synthesis tool - -BROKEN= "fails to compile - missing definition of TIME_FMT" USE_BISON= yes USE_GMAKE= yes --- Makefile.patch ends here --- --- pkg-plist.patch begins here --- ---pkg-plist Sat Nov 15 14:07:23 2003 +++ pkg-plist Thu Dec 11 22:05:44 2003 @@ -5,14 +5,24 @@ include/ivl_target.h include/veriuser.h include/vpi_user.h +include/_pli_types.h lib/ivl/cadpli.vpl +lib/ivl/fpga-s.conf +lib/ivl/fpga.conf lib/ivl/fpga.tgt -lib/ivl/iverilog.conf lib/ivl/ivl lib/ivl/ivlpp +lib/ivl/null-s.conf +lib/ivl/null.conf lib/ivl/null.tgt lib/ivl/system.vpi +lib/ivl/vvp-s.conf +lib/ivl/vvp.conf lib/ivl/vvp.tgt +lib/ivl/xnf-s.conf +lib/ivl/xnf.conf lib/libveriuser.a lib/libvpi.a +man/man1/iverilog-fpga.1 @dirrm lib/ivl --- pkg-plist.patch ends here --- >Release-Note: >Audit-Trail: >Unformatted:
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