Date: 29 Jun 96 07:50:18 PDT (Sat) From: mrm@Sceard.COM (M.R.Murphy) To: freebsd-hardware@freefall.freebsd.org Cc: admin@ftcnet.com, mrm@marmot.mole.org Subject: Re: Hi-speed serial input for Pagesat HS-2000? Message-ID: <9606290750.AA17683@Sceard.COM>
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>was Re: muliport boards - building a PPP dialup server
>On Sat, 29 Jun 1996, Jacob M. Parnas wrote:
>
>> >> I'm confused. I thought the 16550 was good up to 115,200 baud, but when
>> >> ISDN eventually takes over with compression, ~512kbaud will be the norm.
>> >> I don't know if they can handle that...
>> >
>> The TI 17550 can go up to 900kbaud/second, which is a new UART.
>>
>> I've seen a PC Card that costs $199-$319 depending on who you are,
>> and it does everything with a UART on top (the software driver for
>> BSDI will be $95.
>
>I'm having trouble with receive overruns with the 115.2 Kb/s news
>feed from the new Pagesat HS-2000. I'm using a Lava ISA 16C550-
>based com port on a 486DX4-100, 64 MB RAM, BSDI V2.1 news server.
>I talked to 'Mike' at Pagesat who recommended a DOS-based PC as
>a dedicated input spooler which would then feed the BSDI news
>server.
> This seems like an extravagant 'kludge'. I checked
>around a found a couple of external serial buffer boxes, but
>they wouldn't work faster than 38.4 Kb/s. CyberResearch has
>a hi-speed buffered serial card, but it's designed for output
>spooling.
> I think what I need is a hi-speed buffered input serial
>card that's compatible with the Pagesat psfrx program. I think
>16 or 32 bytes of FIFO is not nearly enough since the Pagesat
>data receiver does no flow control. Ideas, suggestions or product
>source would be welcome.
>
>Bernard Klatt Owner Fairview Tech Ctr Ltd. www.ftcnet.com
>
Change the lines in sio.c that now read
com->ftl_init = FIFO_TRIGGER_14;
and
? FIFO_TRIGGER_1 : FIFO_TRIGGER_8;
to
com->ftl_init = FIFO_TRIGGER_8;
and
? FIFO_TRIGGER_1 : FIFO_TRIGGER_8;
and then rebuild your system and see if you still get overruns. This will
increase the interrupt load but will also give more time to service
the interrupt before FIFO overrun occurs. A 486DX4/100 should be
able to handle the increased load without problems.
This is an alternative to either
1) change the #ifdef so that the FIFO_TRIGGER_DELTA code is again active
even though it is non optimally placed, or
2) putting the FIFO_TRIGGER_DELTA code in the right place.
I know it's not the best solution, but it's better than no solution.
It would be nice to have this in the source such that it could be a
parameter selected at configuration time.
--
Mike Murphy mrm@Sceard.COM ucsd!sceard!mrm +1 619 598 5874
Better is the enemy of Good
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