Date: Fri, 3 Jan 1997 14:28:06 +0100 (MET) From: grog@lemis.de To: msmith@atrad.adelaide.edu.au (Michael Smith) Cc: hackers@freebsd.org (FreeBSD Hackers) Subject: Re: Ints (fwd) Message-ID: <199701031328.OAA14921@freebie.lemis.de> In-Reply-To: <199701020100.LAA14579@genesis.atrad.adelaide.edu.au> from Michael Smith at "Jan 2, 97 11:30:54 am"
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Michael Smith writes:
> hmmm stands accused of saying:
>>
>> Wait a second guys.... The interrupt lines on the ISA bus are
>> open-collector, which means that it is possible to OR-TIE them
>> together- remember Digital Electronics Fundamentals? Open-collector
>> is very similar to tri-state, and is used when there is only 1
>> active state. If an application should require multiple devices to
>> share a bus, and 2 active states are required, then tri-state
>> drivers are required on all outputs.
>
> ... only ISA interrupt lines aren't open-collector. The RC time
> constant implicit in OC circuits (there is a tradeoff between the
> risetime and the power dissipation in the driving circuit) is
> unacceptable for anything other than the slowest logic.
>
> Just about every other multi-card bus ever invented uses daisy-chained
> interrupts or slot interrupts or some other manifestation of a sensible
> scheme. But not ISA. YOU CANNOT SHARE INTERRUPTS SAFELY ON ISA.
Well, I don't know if I consider daisy-chaining sensible either. But
the biggest problem with interrupt sharing on ISA used to be the
brain-dead circuitry of the UART board, not the bus nor the UART
itself. The circuits I have show that the interrupt output of the
UART goes to the *input* of an LS125 tri-state buffer, which then goes
via a DIP switch to the IRQ3*/IRQ4* lines. The enable input (active
low) of the LS125 gate is driven by OUT2*, which is effectively the
"interrupt enable" bit of the modem control register.
The problem with this is that the gate drives the IRQ line at all
times, which isn't what tri-state is all about. The correct thing
would have been to use the logical 'and' of OUT2* and INTRPT to enable
the LS125 to pull the interrupt line down, but that would have
required at least another LS00 gate. The way it is now, if you
connect two of this kind of UART board to the bus, they'll fight every
time there's an interrupt, and the stronger will win.
To be fair, this is the way it used to be. Nowadays you don't get
many circuit diagrams with your hardware, and it's possible that
somebody has recognized the idiocy of this circuit, and has done
something about it. But:
1. I'm sure not everybody has done so.
2. The marketing people wouldn't understand it, so they wouldn't
document it.
>> The only state which we are concerned with is ACTIVE (low). The
>> processor doesn't care if an interrupt isn't happening, only when
>> one IS. So a peripheral device does not DRIVE the interrupt line
>> "the other way", it simply de-activates it's open-collector output.
>> If another peripheral device happens to have interrupt asserted, the
>> state of the IRQ line will not change.
>
> ... but the inputs to the 8259 are _edge_triggered_. If another
> device is holding the line asserted, that doesn't count for a new
> interrupt. It also means that another edge can't occur. So not only
> is the second interrupt lost, but every interrupt after that is lost
> as well.
I thought the interrupt was just a pulse. It certainly was on the
8251.
Greg
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