Date: Fri, 11 Dec 2015 16:51:04 +0000 (UTC) From: Warner Losh <imp@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r292114 - head/sys/mips/include Message-ID: <201512111651.tBBGp4er030950@repo.freebsd.org>
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Author: imp Date: Fri Dec 11 16:51:04 2015 New Revision: 292114 URL: https://svnweb.freebsd.org/changeset/base/292114 Log: Correct the CONFIG0_VI value. According to http://www.t-es-t.hu/download/mips/md00090c.pdf this is bit 3 of the config0 word, not bit 2. This should fix virtually indexed caches (relatively new in the MIPS world, so no current platforms used this and current code just uses it as an optimization). It was causing false positives on newer platforms that default to large values for the kseg0 cache coherency attribute. Submitted by: Stanislav Galabov PR: 205249 Modified: head/sys/mips/include/cpuregs.h Modified: head/sys/mips/include/cpuregs.h ============================================================================== --- head/sys/mips/include/cpuregs.h Fri Dec 11 15:35:47 2015 (r292113) +++ head/sys/mips/include/cpuregs.h Fri Dec 11 16:51:04 2015 (r292114) @@ -524,7 +524,7 @@ #define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */ #define MIPS_CONFIG0_MT_SHIFT 7 #define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */ -#define MIPS_CONFIG0_VI 0x00000004 /* instruction cache is virtual */ +#define MIPS_CONFIG0_VI 0x00000008 /* instruction cache is virtual */ #define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */ #define MIPS_CONFIG1_TLBSZ_SHIFT 25
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