Date: Fri, 7 Aug 2015 23:01:35 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r286425 - in vendor/llvm/dist: . autoconf bindings/python/llvm cmake/modules docs include/llvm include/llvm-c include/llvm/ADT include/llvm/Analysis include/llvm/Bitcode include/llvm/Co... Message-ID: <201508072301.t77N1ZqE093289@repo.freebsd.org>
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Author: dim Date: Fri Aug 7 23:01:33 2015 New Revision: 286425 URL: https://svnweb.freebsd.org/changeset/base/286425 Log: Vendor import of llvm trunk r242221: https://llvm.org/svn/llvm-project/llvm/trunk@242221 Added: vendor/llvm/dist/include/llvm/IR/IntrinsicsWebAssembly.td vendor/llvm/dist/include/llvm/Transforms/Utils/LoopVersioning.h (contents, props changed) vendor/llvm/dist/lib/MC/MCSchedule.cpp (contents, props changed) vendor/llvm/dist/lib/Target/Hexagon/BitTracker.cpp (contents, props changed) vendor/llvm/dist/lib/Target/Hexagon/BitTracker.h (contents, props changed) vendor/llvm/dist/lib/Target/Hexagon/HexagonBitTracker.cpp (contents, props changed) vendor/llvm/dist/lib/Target/Hexagon/HexagonBitTracker.h (contents, props changed) vendor/llvm/dist/lib/Target/Hexagon/HexagonCommonGEP.cpp (contents, props changed) vendor/llvm/dist/lib/Target/Hexagon/HexagonGenExtract.cpp (contents, props changed) vendor/llvm/dist/lib/Target/Hexagon/HexagonGenInsert.cpp (contents, props changed) vendor/llvm/dist/lib/Target/Hexagon/HexagonGenPredicate.cpp (contents, props changed) vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyInstrCall.td vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyInstrConv.td vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyInstrFloat.td vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyInstrInteger.td vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyInstrMemory.td vendor/llvm/dist/lib/Transforms/IPO/ElimAvailExtern.cpp (contents, props changed) vendor/llvm/dist/lib/Transforms/Utils/LoopVersioning.cpp (contents, props changed) vendor/llvm/dist/test/Analysis/LoopAccessAnalysis/pointer-with-unknown-bounds.ll vendor/llvm/dist/test/Bitcode/fcmp-fast.ll vendor/llvm/dist/test/CodeGen/AArch64/arm64-nvcast.ll vendor/llvm/dist/test/CodeGen/AArch64/nest-register.ll vendor/llvm/dist/test/CodeGen/AArch64/xbfiz.ll vendor/llvm/dist/test/CodeGen/AMDGPU/ds_read2_superreg.ll vendor/llvm/dist/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll vendor/llvm/dist/test/CodeGen/AMDGPU/v_mac.ll vendor/llvm/dist/test/CodeGen/ARM/Windows/trivial-gnu-object.ll vendor/llvm/dist/test/CodeGen/ARM/cttz.ll vendor/llvm/dist/test/CodeGen/ARM/cttz_vector.ll vendor/llvm/dist/test/CodeGen/ARM/nest-register.ll vendor/llvm/dist/test/CodeGen/ARM/subtarget-features-long-calls.ll vendor/llvm/dist/test/CodeGen/Generic/run-pass.ll vendor/llvm/dist/test/CodeGen/Hexagon/Atomics.ll vendor/llvm/dist/test/CodeGen/Hexagon/common-gep-basic.ll vendor/llvm/dist/test/CodeGen/Hexagon/common-gep-icm.ll vendor/llvm/dist/test/CodeGen/Hexagon/extract-basic.ll vendor/llvm/dist/test/CodeGen/Hexagon/insert-basic.ll vendor/llvm/dist/test/CodeGen/Hexagon/predicate-logical.ll vendor/llvm/dist/test/CodeGen/Hexagon/predicate-rcmp.ll vendor/llvm/dist/test/CodeGen/MIR/X86/basic-block-liveins.mir vendor/llvm/dist/test/CodeGen/MIR/X86/dead-register-flag.mir vendor/llvm/dist/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir vendor/llvm/dist/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir vendor/llvm/dist/test/CodeGen/MIR/X86/expected-named-register-livein.mir vendor/llvm/dist/test/CodeGen/MIR/X86/expected-register-after-flags.mir vendor/llvm/dist/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir vendor/llvm/dist/test/CodeGen/MIR/X86/fixed-stack-objects.mir vendor/llvm/dist/test/CodeGen/MIR/X86/implicit-register-flag.mir vendor/llvm/dist/test/CodeGen/MIR/X86/killed-register-flag.mir vendor/llvm/dist/test/CodeGen/MIR/X86/missing-implicit-operand.mir vendor/llvm/dist/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir vendor/llvm/dist/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir vendor/llvm/dist/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir vendor/llvm/dist/test/CodeGen/MIR/X86/stack-objects.mir vendor/llvm/dist/test/CodeGen/MIR/X86/subregister-operands.mir vendor/llvm/dist/test/CodeGen/MIR/X86/undef-register-flag.mir vendor/llvm/dist/test/CodeGen/MIR/X86/undefined-register-class.mir vendor/llvm/dist/test/CodeGen/MIR/X86/undefined-virtual-register.mir vendor/llvm/dist/test/CodeGen/MIR/X86/unknown-subregister-index.mir vendor/llvm/dist/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir vendor/llvm/dist/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir vendor/llvm/dist/test/CodeGen/MIR/X86/virtual-registers.mir vendor/llvm/dist/test/CodeGen/MIR/frame-info.mir vendor/llvm/dist/test/CodeGen/MIR/machine-function-missing-body-error.mir vendor/llvm/dist/test/CodeGen/NVPTX/loop-vectorize.ll vendor/llvm/dist/test/CodeGen/NVPTX/lower-aggr-copies.ll vendor/llvm/dist/test/CodeGen/PowerPC/ppc32-nest.ll vendor/llvm/dist/test/CodeGen/PowerPC/ppc64-nest.ll vendor/llvm/dist/test/CodeGen/PowerPC/swaps-le-5.ll vendor/llvm/dist/test/CodeGen/SPARC/multiple-div.ll vendor/llvm/dist/test/CodeGen/WebAssembly/ vendor/llvm/dist/test/CodeGen/WebAssembly/lit.local.cfg vendor/llvm/dist/test/CodeGen/WinEH/cppeh-catch-all-win32.ll vendor/llvm/dist/test/CodeGen/WinEH/seh-exception-code.ll vendor/llvm/dist/test/CodeGen/WinEH/seh-exception-code2.ll vendor/llvm/dist/test/CodeGen/WinEH/seh-outlined-finally-win32.ll vendor/llvm/dist/test/CodeGen/X86/cppeh-nounwind.ll vendor/llvm/dist/test/CodeGen/X86/eh-nolandingpads.ll vendor/llvm/dist/test/CodeGen/X86/frameregister.ll vendor/llvm/dist/test/CodeGen/X86/inline-asm-bad-constraint-n.ll vendor/llvm/dist/test/CodeGen/X86/legalize-shl-vec.ll vendor/llvm/dist/test/CodeGen/X86/read-fp-no-frame-pointer.ll vendor/llvm/dist/test/CodeGen/X86/seh-stack-realign-win32.ll vendor/llvm/dist/test/CodeGen/X86/seh-stack-realign.ll vendor/llvm/dist/test/CodeGen/X86/vector-shuffle-sse4a.ll vendor/llvm/dist/test/CodeGen/X86/webkit-jscc.ll vendor/llvm/dist/test/ExecutionEngine/RuntimeDyld/Mips/ELF_O32R6_relocations.s (contents, props changed) vendor/llvm/dist/test/LibDriver/infer-output-path.test vendor/llvm/dist/test/MC/COFF/safeseh.s (contents, props changed) vendor/llvm/dist/test/MC/ELF/relax-arith4.s (contents, props changed) vendor/llvm/dist/test/MC/Mips/macro-la-bad.s (contents, props changed) vendor/llvm/dist/test/MC/Mips/macro-la.s (contents, props changed) vendor/llvm/dist/test/MC/Mips/macro-li-bad.s (contents, props changed) vendor/llvm/dist/test/MC/Mips/macro-li.s (contents, props changed) vendor/llvm/dist/test/Object/Inputs/elf-mip64-reloc.o (contents, props changed) vendor/llvm/dist/test/Object/Inputs/invalid-bad-section-address.coff (contents, props changed) vendor/llvm/dist/test/Object/Inputs/no-section-table.so (contents, props changed) vendor/llvm/dist/test/Object/Inputs/symtab-only.a (contents, props changed) vendor/llvm/dist/test/Object/Inputs/thin-path.a (contents, props changed) vendor/llvm/dist/test/Object/Inputs/trivial-object-test2.macho-x86-64 (contents, props changed) vendor/llvm/dist/test/Object/Mips/reloc-visit.test vendor/llvm/dist/test/Object/X86/nm-coff.s (contents, props changed) vendor/llvm/dist/test/Object/X86/nm-macho.s (contents, props changed) vendor/llvm/dist/test/Object/archive-extract.test vendor/llvm/dist/test/Object/coff-invalid.test vendor/llvm/dist/test/Object/no-section-table.test vendor/llvm/dist/test/Object/yaml2obj-elf-alignment.yaml vendor/llvm/dist/test/Transforms/EliminateAvailableExternally/ vendor/llvm/dist/test/Transforms/EliminateAvailableExternally/visibility.ll vendor/llvm/dist/test/Transforms/GVN/pre-new-inst.ll vendor/llvm/dist/test/Transforms/IndVarSimplify/lrev-existing-umin.ll vendor/llvm/dist/test/Transforms/InstCombine/load-combine-metadata.ll vendor/llvm/dist/test/Transforms/InstCombine/load_combine_aa.ll vendor/llvm/dist/test/Transforms/LICM/PR24013.ll vendor/llvm/dist/test/Transforms/LoopIdiom/ctpop-multiple-users-crash.ll vendor/llvm/dist/test/Transforms/LoopRotate/oz-disable.ll vendor/llvm/dist/test/Transforms/LoopStrengthReduce/ephemeral.ll vendor/llvm/dist/test/Verifier/comdat-decl1.ll vendor/llvm/dist/test/Verifier/comdat-decl2.ll vendor/llvm/dist/test/tools/llvm-readobj/Inputs/got-plt.exe.elf-mipsel (contents, props changed) vendor/llvm/dist/test/tools/llvm-readobj/mips-plt.test Deleted: vendor/llvm/dist/include/llvm/Analysis/JumpInstrTableInfo.h vendor/llvm/dist/lib/Target/MSP430/MSP430SelectionDAGInfo.cpp vendor/llvm/dist/lib/Target/MSP430/MSP430SelectionDAGInfo.h vendor/llvm/dist/lib/Target/Mips/MipsSelectionDAGInfo.cpp vendor/llvm/dist/lib/Target/Mips/MipsSelectionDAGInfo.h vendor/llvm/dist/lib/Target/PowerPC/PPCSelectionDAGInfo.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCSelectionDAGInfo.h vendor/llvm/dist/lib/Target/Sparc/SparcSelectionDAGInfo.cpp vendor/llvm/dist/lib/Target/Sparc/SparcSelectionDAGInfo.h vendor/llvm/dist/test/CodeGen/ARM/ctz.ll vendor/llvm/dist/test/Object/extract.ll Modified: vendor/llvm/dist/.gitignore vendor/llvm/dist/autoconf/config.guess vendor/llvm/dist/bindings/python/llvm/object.py vendor/llvm/dist/cmake/modules/AddLLVM.cmake vendor/llvm/dist/docs/ExceptionHandling.rst vendor/llvm/dist/docs/LangRef.rst vendor/llvm/dist/docs/ProgrammersManual.rst vendor/llvm/dist/docs/StackMaps.rst vendor/llvm/dist/include/llvm-c/Core.h vendor/llvm/dist/include/llvm-c/Object.h vendor/llvm/dist/include/llvm-c/lto.h vendor/llvm/dist/include/llvm/ADT/APFloat.h vendor/llvm/dist/include/llvm/ADT/Triple.h vendor/llvm/dist/include/llvm/ADT/edit_distance.h vendor/llvm/dist/include/llvm/Analysis/AliasAnalysis.h vendor/llvm/dist/include/llvm/Analysis/ConstantFolding.h vendor/llvm/dist/include/llvm/Analysis/DominanceFrontier.h vendor/llvm/dist/include/llvm/Analysis/IVUsers.h vendor/llvm/dist/include/llvm/Analysis/InstructionSimplify.h vendor/llvm/dist/include/llvm/Analysis/LibCallSemantics.h vendor/llvm/dist/include/llvm/Analysis/LoopAccessAnalysis.h vendor/llvm/dist/include/llvm/Analysis/LoopInfo.h vendor/llvm/dist/include/llvm/Analysis/RegionInfo.h vendor/llvm/dist/include/llvm/Analysis/TargetTransformInfo.h vendor/llvm/dist/include/llvm/Analysis/TargetTransformInfoImpl.h vendor/llvm/dist/include/llvm/Analysis/VectorUtils.h vendor/llvm/dist/include/llvm/Bitcode/LLVMBitCodes.h vendor/llvm/dist/include/llvm/Bitcode/ReaderWriter.h vendor/llvm/dist/include/llvm/CodeGen/Analysis.h vendor/llvm/dist/include/llvm/CodeGen/BasicTTIImpl.h vendor/llvm/dist/include/llvm/CodeGen/CommandFlags.h vendor/llvm/dist/include/llvm/CodeGen/ISDOpcodes.h vendor/llvm/dist/include/llvm/CodeGen/LiveIntervalUnion.h vendor/llvm/dist/include/llvm/CodeGen/LiveRegMatrix.h vendor/llvm/dist/include/llvm/CodeGen/MIRYamlMapping.h vendor/llvm/dist/include/llvm/CodeGen/MachineConstantPool.h vendor/llvm/dist/include/llvm/CodeGen/MachineDominators.h vendor/llvm/dist/include/llvm/CodeGen/MachineFrameInfo.h vendor/llvm/dist/include/llvm/CodeGen/MachineFunction.h vendor/llvm/dist/include/llvm/CodeGen/MachineLoopInfo.h vendor/llvm/dist/include/llvm/CodeGen/MachineModuleInfo.h vendor/llvm/dist/include/llvm/CodeGen/MachineRegionInfo.h vendor/llvm/dist/include/llvm/CodeGen/MachineRegisterInfo.h vendor/llvm/dist/include/llvm/CodeGen/Passes.h vendor/llvm/dist/include/llvm/CodeGen/RegisterPressure.h vendor/llvm/dist/include/llvm/CodeGen/SelectionDAG.h vendor/llvm/dist/include/llvm/CodeGen/SelectionDAGNodes.h vendor/llvm/dist/include/llvm/CodeGen/StackMaps.h vendor/llvm/dist/include/llvm/CodeGen/WinEHFuncInfo.h vendor/llvm/dist/include/llvm/ExecutionEngine/ExecutionEngine.h vendor/llvm/dist/include/llvm/ExecutionEngine/RuntimeDyld.h vendor/llvm/dist/include/llvm/IR/Attributes.h vendor/llvm/dist/include/llvm/IR/CallSite.h vendor/llvm/dist/include/llvm/IR/DIBuilder.h vendor/llvm/dist/include/llvm/IR/DebugInfoMetadata.h vendor/llvm/dist/include/llvm/IR/Dominators.h vendor/llvm/dist/include/llvm/IR/Function.h vendor/llvm/dist/include/llvm/IR/GlobalValue.h vendor/llvm/dist/include/llvm/IR/IRBuilder.h vendor/llvm/dist/include/llvm/IR/Instruction.h vendor/llvm/dist/include/llvm/IR/Instructions.h vendor/llvm/dist/include/llvm/IR/Intrinsics.td vendor/llvm/dist/include/llvm/IR/IntrinsicsPowerPC.td vendor/llvm/dist/include/llvm/IR/IntrinsicsX86.td vendor/llvm/dist/include/llvm/IR/Operator.h vendor/llvm/dist/include/llvm/IR/Value.h vendor/llvm/dist/include/llvm/InitializePasses.h vendor/llvm/dist/include/llvm/LinkAllPasses.h vendor/llvm/dist/include/llvm/MC/MCContext.h vendor/llvm/dist/include/llvm/MC/MCDwarf.h vendor/llvm/dist/include/llvm/MC/MCInstrDesc.h vendor/llvm/dist/include/llvm/MC/MCSchedule.h vendor/llvm/dist/include/llvm/MC/MCSubtargetInfo.h vendor/llvm/dist/include/llvm/MC/MCSymbol.h vendor/llvm/dist/include/llvm/MC/MCSymbolMachO.h vendor/llvm/dist/include/llvm/MC/MCTargetOptions.h vendor/llvm/dist/include/llvm/Object/Archive.h vendor/llvm/dist/include/llvm/Object/ArchiveWriter.h vendor/llvm/dist/include/llvm/Object/COFF.h vendor/llvm/dist/include/llvm/Object/ELF.h vendor/llvm/dist/include/llvm/Object/ELFObjectFile.h vendor/llvm/dist/include/llvm/Object/ELFTypes.h vendor/llvm/dist/include/llvm/Object/ELFYAML.h vendor/llvm/dist/include/llvm/Object/MachO.h vendor/llvm/dist/include/llvm/Object/ObjectFile.h vendor/llvm/dist/include/llvm/Object/RelocVisitor.h vendor/llvm/dist/include/llvm/Object/SymbolicFile.h vendor/llvm/dist/include/llvm/Support/COFF.h vendor/llvm/dist/include/llvm/Support/CommandLine.h vendor/llvm/dist/include/llvm/Support/Compiler.h vendor/llvm/dist/include/llvm/Support/OnDiskHashTable.h vendor/llvm/dist/include/llvm/Support/TargetRegistry.h vendor/llvm/dist/include/llvm/Support/raw_ostream.h vendor/llvm/dist/include/llvm/TableGen/Record.h vendor/llvm/dist/include/llvm/Target/Target.td vendor/llvm/dist/include/llvm/Target/TargetFrameLowering.h vendor/llvm/dist/include/llvm/Target/TargetLowering.h vendor/llvm/dist/include/llvm/Target/TargetMachine.h vendor/llvm/dist/include/llvm/Target/TargetOpcodes.h vendor/llvm/dist/include/llvm/Target/TargetSelectionDAGInfo.h vendor/llvm/dist/include/llvm/Target/TargetSubtargetInfo.h vendor/llvm/dist/include/llvm/Transforms/IPO.h vendor/llvm/dist/include/llvm/Transforms/IPO/PassManagerBuilder.h vendor/llvm/dist/include/llvm/Transforms/Utils/Cloning.h vendor/llvm/dist/lib/Analysis/AliasAnalysis.cpp vendor/llvm/dist/lib/Analysis/AliasDebugger.cpp vendor/llvm/dist/lib/Analysis/AliasSetTracker.cpp vendor/llvm/dist/lib/Analysis/BasicAliasAnalysis.cpp vendor/llvm/dist/lib/Analysis/ConstantFolding.cpp vendor/llvm/dist/lib/Analysis/IPA/GlobalsModRef.cpp vendor/llvm/dist/lib/Analysis/IPA/InlineCost.cpp vendor/llvm/dist/lib/Analysis/IVUsers.cpp vendor/llvm/dist/lib/Analysis/InstructionSimplify.cpp vendor/llvm/dist/lib/Analysis/LoopAccessAnalysis.cpp vendor/llvm/dist/lib/Analysis/NoAliasAnalysis.cpp vendor/llvm/dist/lib/Analysis/TargetTransformInfo.cpp vendor/llvm/dist/lib/Analysis/ValueTracking.cpp vendor/llvm/dist/lib/Analysis/VectorUtils.cpp vendor/llvm/dist/lib/AsmParser/LLLexer.cpp vendor/llvm/dist/lib/AsmParser/LLParser.cpp vendor/llvm/dist/lib/AsmParser/LLToken.h vendor/llvm/dist/lib/Bitcode/Reader/BitcodeReader.cpp vendor/llvm/dist/lib/Bitcode/Writer/BitcodeWriter.cpp vendor/llvm/dist/lib/CodeGen/Analysis.cpp vendor/llvm/dist/lib/CodeGen/AsmPrinter/ARMException.cpp vendor/llvm/dist/lib/CodeGen/AsmPrinter/AsmPrinter.cpp vendor/llvm/dist/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp vendor/llvm/dist/lib/CodeGen/AsmPrinter/DwarfDebug.h vendor/llvm/dist/lib/CodeGen/AsmPrinter/DwarfUnit.h vendor/llvm/dist/lib/CodeGen/AsmPrinter/EHStreamer.cpp vendor/llvm/dist/lib/CodeGen/AsmPrinter/WinCodeViewLineTables.cpp vendor/llvm/dist/lib/CodeGen/AsmPrinter/WinCodeViewLineTables.h vendor/llvm/dist/lib/CodeGen/AsmPrinter/WinException.cpp vendor/llvm/dist/lib/CodeGen/BasicTargetTransformInfo.cpp vendor/llvm/dist/lib/CodeGen/CodeGenPrepare.cpp vendor/llvm/dist/lib/CodeGen/DeadMachineInstructionElim.cpp vendor/llvm/dist/lib/CodeGen/ExecutionDepsFix.cpp vendor/llvm/dist/lib/CodeGen/GlobalMerge.cpp vendor/llvm/dist/lib/CodeGen/ImplicitNullChecks.cpp vendor/llvm/dist/lib/CodeGen/LLVMTargetMachine.cpp vendor/llvm/dist/lib/CodeGen/LiveRegMatrix.cpp vendor/llvm/dist/lib/CodeGen/MIRParser/MILexer.cpp vendor/llvm/dist/lib/CodeGen/MIRParser/MILexer.h vendor/llvm/dist/lib/CodeGen/MIRParser/MIParser.cpp vendor/llvm/dist/lib/CodeGen/MIRParser/MIParser.h vendor/llvm/dist/lib/CodeGen/MIRParser/MIRParser.cpp vendor/llvm/dist/lib/CodeGen/MIRPrinter.cpp vendor/llvm/dist/lib/CodeGen/MachineDominators.cpp vendor/llvm/dist/lib/CodeGen/MachineFunction.cpp vendor/llvm/dist/lib/CodeGen/MachineModuleInfo.cpp vendor/llvm/dist/lib/CodeGen/MachineRegisterInfo.cpp vendor/llvm/dist/lib/CodeGen/MachineTraceMetrics.cpp vendor/llvm/dist/lib/CodeGen/Passes.cpp vendor/llvm/dist/lib/CodeGen/PrologEpilogInserter.cpp vendor/llvm/dist/lib/CodeGen/RegAllocFast.cpp vendor/llvm/dist/lib/CodeGen/RegAllocGreedy.cpp vendor/llvm/dist/lib/CodeGen/RegisterPressure.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/DAGCombiner.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/FastISel.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/InstrEmitter.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeTypes.h vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAG.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/StatepointLowering.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/TargetLowering.cpp vendor/llvm/dist/lib/CodeGen/SelectionDAG/TargetSelectionDAGInfo.cpp vendor/llvm/dist/lib/CodeGen/SjLjEHPrepare.cpp vendor/llvm/dist/lib/CodeGen/StackMapLivenessAnalysis.cpp vendor/llvm/dist/lib/CodeGen/StackMaps.cpp vendor/llvm/dist/lib/CodeGen/StackProtector.cpp vendor/llvm/dist/lib/CodeGen/TargetFrameLoweringImpl.cpp vendor/llvm/dist/lib/CodeGen/TargetLoweringBase.cpp vendor/llvm/dist/lib/CodeGen/TwoAddressInstructionPass.cpp vendor/llvm/dist/lib/CodeGen/VirtRegMap.cpp vendor/llvm/dist/lib/CodeGen/WinEHPrepare.cpp vendor/llvm/dist/lib/DebugInfo/DWARF/DWARFContext.cpp vendor/llvm/dist/lib/ExecutionEngine/IntelJITEvents/CMakeLists.txt vendor/llvm/dist/lib/ExecutionEngine/IntelJITEvents/IntelJITEventListener.cpp vendor/llvm/dist/lib/ExecutionEngine/IntelJITEvents/LLVMBuild.txt vendor/llvm/dist/lib/ExecutionEngine/OProfileJIT/LLVMBuild.txt vendor/llvm/dist/lib/ExecutionEngine/OProfileJIT/OProfileJITEventListener.cpp vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldChecker.cpp vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOI386.h vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOX86_64.h vendor/llvm/dist/lib/IR/Attributes.cpp vendor/llvm/dist/lib/IR/AutoUpgrade.cpp vendor/llvm/dist/lib/IR/BasicBlock.cpp vendor/llvm/dist/lib/IR/Core.cpp vendor/llvm/dist/lib/IR/DIBuilder.cpp vendor/llvm/dist/lib/IR/Dominators.cpp vendor/llvm/dist/lib/IR/Value.cpp vendor/llvm/dist/lib/IR/Verifier.cpp vendor/llvm/dist/lib/LTO/LTOModule.cpp vendor/llvm/dist/lib/LibDriver/LibDriver.cpp vendor/llvm/dist/lib/MC/CMakeLists.txt vendor/llvm/dist/lib/MC/MCAsmStreamer.cpp vendor/llvm/dist/lib/MC/MCAssembler.cpp vendor/llvm/dist/lib/MC/MCDisassembler/MCExternalSymbolizer.cpp vendor/llvm/dist/lib/MC/MCInstrDesc.cpp vendor/llvm/dist/lib/MC/MCSubtargetInfo.cpp vendor/llvm/dist/lib/MC/MCSymbol.cpp vendor/llvm/dist/lib/Object/Archive.cpp vendor/llvm/dist/lib/Object/ArchiveWriter.cpp vendor/llvm/dist/lib/Object/COFFObjectFile.cpp vendor/llvm/dist/lib/Object/ELFYAML.cpp vendor/llvm/dist/lib/Object/MachOObjectFile.cpp vendor/llvm/dist/lib/Object/Object.cpp vendor/llvm/dist/lib/Object/ObjectFile.cpp vendor/llvm/dist/lib/Support/APFloat.cpp vendor/llvm/dist/lib/Support/CommandLine.cpp vendor/llvm/dist/lib/Support/Triple.cpp vendor/llvm/dist/lib/TableGen/Record.cpp vendor/llvm/dist/lib/TableGen/SetTheory.cpp vendor/llvm/dist/lib/TableGen/TGParser.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64CallingConvention.td vendor/llvm/dist/lib/Target/AArch64/AArch64FastISel.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64FrameLowering.h vendor/llvm/dist/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64ISelLowering.h vendor/llvm/dist/lib/Target/AArch64/AArch64InstrInfo.td vendor/llvm/dist/lib/Target/AArch64/AArch64RegisterInfo.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64SelectionDAGInfo.h vendor/llvm/dist/lib/Target/AArch64/AArch64Subtarget.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64TargetTransformInfo.cpp vendor/llvm/dist/lib/Target/AArch64/AArch64TargetTransformInfo.h vendor/llvm/dist/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp vendor/llvm/dist/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp vendor/llvm/dist/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp vendor/llvm/dist/lib/Target/AMDGPU/AMDGPU.td vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUISelLowering.cpp vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUISelLowering.h vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUSubtarget.cpp vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUSubtarget.h vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp vendor/llvm/dist/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h vendor/llvm/dist/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp vendor/llvm/dist/lib/Target/AMDGPU/R600ISelLowering.cpp vendor/llvm/dist/lib/Target/AMDGPU/R600ISelLowering.h vendor/llvm/dist/lib/Target/AMDGPU/SIFoldOperands.cpp vendor/llvm/dist/lib/Target/AMDGPU/SIISelLowering.cpp vendor/llvm/dist/lib/Target/AMDGPU/SIISelLowering.h vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.cpp vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.h vendor/llvm/dist/lib/Target/AMDGPU/SIInstrInfo.td vendor/llvm/dist/lib/Target/AMDGPU/SIInstructions.td vendor/llvm/dist/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp vendor/llvm/dist/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp vendor/llvm/dist/lib/Target/AMDGPU/SIPrepareScratchRegs.cpp vendor/llvm/dist/lib/Target/AMDGPU/SIRegisterInfo.cpp vendor/llvm/dist/lib/Target/AMDGPU/SIShrinkInstructions.cpp vendor/llvm/dist/lib/Target/ARM/ARM.td vendor/llvm/dist/lib/Target/ARM/ARMBaseInstrInfo.cpp vendor/llvm/dist/lib/Target/ARM/ARMBaseRegisterInfo.cpp vendor/llvm/dist/lib/Target/ARM/ARMCallingConv.td vendor/llvm/dist/lib/Target/ARM/ARMFastISel.cpp vendor/llvm/dist/lib/Target/ARM/ARMFrameLowering.cpp vendor/llvm/dist/lib/Target/ARM/ARMFrameLowering.h vendor/llvm/dist/lib/Target/ARM/ARMISelDAGToDAG.cpp vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.cpp vendor/llvm/dist/lib/Target/ARM/ARMISelLowering.h vendor/llvm/dist/lib/Target/ARM/ARMInstrInfo.td vendor/llvm/dist/lib/Target/ARM/ARMLoadStoreOptimizer.cpp vendor/llvm/dist/lib/Target/ARM/ARMSelectionDAGInfo.cpp vendor/llvm/dist/lib/Target/ARM/ARMSelectionDAGInfo.h vendor/llvm/dist/lib/Target/ARM/ARMSubtarget.cpp vendor/llvm/dist/lib/Target/ARM/ARMSubtarget.h vendor/llvm/dist/lib/Target/ARM/ARMTargetMachine.cpp vendor/llvm/dist/lib/Target/ARM/ARMTargetTransformInfo.cpp vendor/llvm/dist/lib/Target/ARM/ARMTargetTransformInfo.h vendor/llvm/dist/lib/Target/ARM/AsmParser/ARMAsmParser.cpp vendor/llvm/dist/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp vendor/llvm/dist/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp vendor/llvm/dist/lib/Target/ARM/Thumb1FrameLowering.cpp vendor/llvm/dist/lib/Target/BPF/BPFFrameLowering.cpp vendor/llvm/dist/lib/Target/BPF/BPFFrameLowering.h vendor/llvm/dist/lib/Target/BPF/BPFISelLowering.cpp vendor/llvm/dist/lib/Target/BPF/BPFSubtarget.cpp vendor/llvm/dist/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp vendor/llvm/dist/lib/Target/CppBackend/CPPBackend.cpp vendor/llvm/dist/lib/Target/CppBackend/CPPTargetMachine.h vendor/llvm/dist/lib/Target/Hexagon/CMakeLists.txt vendor/llvm/dist/lib/Target/Hexagon/HexagonExpandCondsets.cpp vendor/llvm/dist/lib/Target/Hexagon/HexagonFrameLowering.cpp vendor/llvm/dist/lib/Target/Hexagon/HexagonFrameLowering.h vendor/llvm/dist/lib/Target/Hexagon/HexagonISelLowering.cpp vendor/llvm/dist/lib/Target/Hexagon/HexagonISelLowering.h vendor/llvm/dist/lib/Target/Hexagon/HexagonRegisterInfo.cpp vendor/llvm/dist/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp vendor/llvm/dist/lib/Target/Hexagon/HexagonSelectionDAGInfo.h vendor/llvm/dist/lib/Target/Hexagon/HexagonSubtarget.cpp vendor/llvm/dist/lib/Target/Hexagon/HexagonTargetMachine.cpp vendor/llvm/dist/lib/Target/Hexagon/LLVMBuild.txt vendor/llvm/dist/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp vendor/llvm/dist/lib/Target/MSP430/CMakeLists.txt vendor/llvm/dist/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp vendor/llvm/dist/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp vendor/llvm/dist/lib/Target/MSP430/MSP430ISelLowering.cpp vendor/llvm/dist/lib/Target/MSP430/MSP430ISelLowering.h vendor/llvm/dist/lib/Target/MSP430/MSP430RegisterInfo.cpp vendor/llvm/dist/lib/Target/MSP430/MSP430Subtarget.cpp vendor/llvm/dist/lib/Target/MSP430/MSP430Subtarget.h vendor/llvm/dist/lib/Target/Mips/AsmParser/MipsAsmParser.cpp vendor/llvm/dist/lib/Target/Mips/CMakeLists.txt vendor/llvm/dist/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp vendor/llvm/dist/lib/Target/Mips/Mips16FrameLowering.cpp vendor/llvm/dist/lib/Target/Mips/Mips16FrameLowering.h vendor/llvm/dist/lib/Target/Mips/Mips16ISelDAGToDAG.cpp vendor/llvm/dist/lib/Target/Mips/Mips16ISelLowering.cpp vendor/llvm/dist/lib/Target/Mips/MipsFastISel.cpp vendor/llvm/dist/lib/Target/Mips/MipsISelDAGToDAG.cpp vendor/llvm/dist/lib/Target/Mips/MipsISelLowering.cpp vendor/llvm/dist/lib/Target/Mips/MipsISelLowering.h vendor/llvm/dist/lib/Target/Mips/MipsSEFrameLowering.cpp vendor/llvm/dist/lib/Target/Mips/MipsSEFrameLowering.h vendor/llvm/dist/lib/Target/Mips/MipsSEISelDAGToDAG.cpp vendor/llvm/dist/lib/Target/Mips/MipsSEISelLowering.cpp vendor/llvm/dist/lib/Target/Mips/MipsSubtarget.cpp vendor/llvm/dist/lib/Target/Mips/MipsSubtarget.h vendor/llvm/dist/lib/Target/Mips/MipsTargetMachine.cpp vendor/llvm/dist/lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp vendor/llvm/dist/lib/Target/NVPTX/NVPTXAsmPrinter.cpp vendor/llvm/dist/lib/Target/NVPTX/NVPTXISelLowering.cpp vendor/llvm/dist/lib/Target/NVPTX/NVPTXISelLowering.h vendor/llvm/dist/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp vendor/llvm/dist/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp vendor/llvm/dist/lib/Target/NVPTX/NVPTXSubtarget.cpp vendor/llvm/dist/lib/Target/NVPTX/NVPTXTargetMachine.cpp vendor/llvm/dist/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp vendor/llvm/dist/lib/Target/NVPTX/NVPTXTargetTransformInfo.h vendor/llvm/dist/lib/Target/PowerPC/CMakeLists.txt vendor/llvm/dist/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCAsmPrinter.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCCTRLoops.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCCallingConv.td vendor/llvm/dist/lib/Target/PowerPC/PPCFastISel.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCFrameLowering.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCFrameLowering.h vendor/llvm/dist/lib/Target/PowerPC/PPCISelDAGToDAG.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCISelLowering.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCISelLowering.h vendor/llvm/dist/lib/Target/PowerPC/PPCInstrInfo.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCInstrInfo.h vendor/llvm/dist/lib/Target/PowerPC/PPCInstrVSX.td vendor/llvm/dist/lib/Target/PowerPC/PPCRegisterInfo.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCScheduleP7.td vendor/llvm/dist/lib/Target/PowerPC/PPCScheduleP8.td vendor/llvm/dist/lib/Target/PowerPC/PPCSubtarget.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCSubtarget.h vendor/llvm/dist/lib/Target/PowerPC/PPCTargetMachine.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCTargetMachine.h vendor/llvm/dist/lib/Target/PowerPC/PPCTargetTransformInfo.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCTargetTransformInfo.h vendor/llvm/dist/lib/Target/PowerPC/PPCVSXFMAMutate.cpp vendor/llvm/dist/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp vendor/llvm/dist/lib/Target/Sparc/CMakeLists.txt vendor/llvm/dist/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp vendor/llvm/dist/lib/Target/Sparc/SparcFrameLowering.cpp vendor/llvm/dist/lib/Target/Sparc/SparcFrameLowering.h vendor/llvm/dist/lib/Target/Sparc/SparcISelDAGToDAG.cpp vendor/llvm/dist/lib/Target/Sparc/SparcISelLowering.cpp vendor/llvm/dist/lib/Target/Sparc/SparcISelLowering.h vendor/llvm/dist/lib/Target/Sparc/SparcInstrAliases.td vendor/llvm/dist/lib/Target/Sparc/SparcInstrInfo.cpp vendor/llvm/dist/lib/Target/Sparc/SparcInstrInfo.td vendor/llvm/dist/lib/Target/Sparc/SparcRegisterInfo.td vendor/llvm/dist/lib/Target/Sparc/SparcSubtarget.cpp vendor/llvm/dist/lib/Target/Sparc/SparcSubtarget.h vendor/llvm/dist/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp vendor/llvm/dist/lib/Target/SystemZ/SystemZFrameLowering.cpp vendor/llvm/dist/lib/Target/SystemZ/SystemZFrameLowering.h vendor/llvm/dist/lib/Target/SystemZ/SystemZISelLowering.cpp vendor/llvm/dist/lib/Target/SystemZ/SystemZISelLowering.h vendor/llvm/dist/lib/Target/SystemZ/SystemZRegisterInfo.cpp vendor/llvm/dist/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp vendor/llvm/dist/lib/Target/SystemZ/SystemZSelectionDAGInfo.h vendor/llvm/dist/lib/Target/SystemZ/SystemZSubtarget.cpp vendor/llvm/dist/lib/Target/SystemZ/SystemZTargetTransformInfo.h vendor/llvm/dist/lib/Target/TargetMachine.cpp vendor/llvm/dist/lib/Target/TargetSubtargetInfo.cpp vendor/llvm/dist/lib/Target/WebAssembly/CMakeLists.txt vendor/llvm/dist/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp vendor/llvm/dist/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h vendor/llvm/dist/lib/Target/WebAssembly/Makefile vendor/llvm/dist/lib/Target/WebAssembly/README.txt vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyInstrFormats.td vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyInstrInfo.td vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyRegisterInfo.td vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.cpp vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblySubtarget.cpp vendor/llvm/dist/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h vendor/llvm/dist/lib/Target/X86/InstPrinter/X86InstComments.cpp vendor/llvm/dist/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp vendor/llvm/dist/lib/Target/X86/MCTargetDesc/X86ELFRelocationInfo.cpp vendor/llvm/dist/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp vendor/llvm/dist/lib/Target/X86/MCTargetDesc/X86MachORelocationInfo.cpp vendor/llvm/dist/lib/Target/X86/Utils/X86ShuffleDecode.cpp vendor/llvm/dist/lib/Target/X86/Utils/X86ShuffleDecode.h vendor/llvm/dist/lib/Target/X86/X86FastISel.cpp vendor/llvm/dist/lib/Target/X86/X86FloatingPoint.cpp vendor/llvm/dist/lib/Target/X86/X86FrameLowering.cpp vendor/llvm/dist/lib/Target/X86/X86FrameLowering.h vendor/llvm/dist/lib/Target/X86/X86ISelDAGToDAG.cpp vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp vendor/llvm/dist/lib/Target/X86/X86ISelLowering.h vendor/llvm/dist/lib/Target/X86/X86InstrAVX512.td vendor/llvm/dist/lib/Target/X86/X86InstrControl.td vendor/llvm/dist/lib/Target/X86/X86InstrFragmentsSIMD.td vendor/llvm/dist/lib/Target/X86/X86InstrInfo.cpp vendor/llvm/dist/lib/Target/X86/X86InstrInfo.td vendor/llvm/dist/lib/Target/X86/X86InstrSSE.td vendor/llvm/dist/lib/Target/X86/X86IntrinsicsInfo.h vendor/llvm/dist/lib/Target/X86/X86MachineFunctionInfo.h vendor/llvm/dist/lib/Target/X86/X86RegisterInfo.cpp vendor/llvm/dist/lib/Target/X86/X86SelectionDAGInfo.cpp vendor/llvm/dist/lib/Target/X86/X86SelectionDAGInfo.h vendor/llvm/dist/lib/Target/X86/X86Subtarget.cpp vendor/llvm/dist/lib/Target/X86/X86Subtarget.h vendor/llvm/dist/lib/Target/X86/X86TargetTransformInfo.cpp vendor/llvm/dist/lib/Target/X86/X86TargetTransformInfo.h vendor/llvm/dist/lib/Target/X86/X86WinEHState.cpp vendor/llvm/dist/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp vendor/llvm/dist/lib/Target/XCore/XCoreFrameLowering.cpp vendor/llvm/dist/lib/Target/XCore/XCoreFrameLowering.h vendor/llvm/dist/lib/Target/XCore/XCoreISelDAGToDAG.cpp vendor/llvm/dist/lib/Target/XCore/XCoreISelLowering.cpp vendor/llvm/dist/lib/Target/XCore/XCoreISelLowering.h vendor/llvm/dist/lib/Target/XCore/XCoreRegisterInfo.cpp vendor/llvm/dist/lib/Target/XCore/XCoreSelectionDAGInfo.cpp vendor/llvm/dist/lib/Target/XCore/XCoreSelectionDAGInfo.h vendor/llvm/dist/lib/Target/XCore/XCoreSubtarget.cpp vendor/llvm/dist/lib/Target/XCore/XCoreTargetMachine.cpp vendor/llvm/dist/lib/Target/XCore/XCoreTargetTransformInfo.h vendor/llvm/dist/lib/Transforms/IPO/ArgumentPromotion.cpp vendor/llvm/dist/lib/Transforms/IPO/CMakeLists.txt vendor/llvm/dist/lib/Transforms/IPO/DeadArgumentElimination.cpp vendor/llvm/dist/lib/Transforms/IPO/ExtractGV.cpp vendor/llvm/dist/lib/Transforms/IPO/IPO.cpp vendor/llvm/dist/lib/Transforms/IPO/PassManagerBuilder.cpp vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineCompares.cpp vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineInternal.h vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp vendor/llvm/dist/lib/Transforms/InstCombine/InstCombineVectorOps.cpp vendor/llvm/dist/lib/Transforms/InstCombine/InstructionCombining.cpp vendor/llvm/dist/lib/Transforms/Scalar/GVN.cpp vendor/llvm/dist/lib/Transforms/Scalar/IndVarSimplify.cpp vendor/llvm/dist/lib/Transforms/Scalar/LICM.cpp vendor/llvm/dist/lib/Transforms/Scalar/LoopDistribute.cpp vendor/llvm/dist/lib/Transforms/Scalar/LoopIdiomRecognize.cpp vendor/llvm/dist/lib/Transforms/Scalar/LoopInterchange.cpp vendor/llvm/dist/lib/Transforms/Scalar/LoopUnrollPass.cpp vendor/llvm/dist/lib/Transforms/Scalar/MergedLoadStoreMotion.cpp vendor/llvm/dist/lib/Transforms/Scalar/PlaceSafepoints.cpp vendor/llvm/dist/lib/Transforms/Scalar/SCCP.cpp vendor/llvm/dist/lib/Transforms/Scalar/SROA.cpp vendor/llvm/dist/lib/Transforms/Utils/BasicBlockUtils.cpp vendor/llvm/dist/lib/Transforms/Utils/CMakeLists.txt vendor/llvm/dist/lib/Transforms/Utils/CloneFunction.cpp vendor/llvm/dist/lib/Transforms/Utils/Local.cpp vendor/llvm/dist/lib/Transforms/Utils/LoopSimplify.cpp vendor/llvm/dist/lib/Transforms/Vectorize/LoopVectorize.cpp vendor/llvm/dist/lib/Transforms/Vectorize/SLPVectorizer.cpp vendor/llvm/dist/test/Analysis/BasicAA/modref.ll vendor/llvm/dist/test/Analysis/CostModel/X86/testshiftashr.ll vendor/llvm/dist/test/Analysis/CostModel/X86/testshiftlshr.ll vendor/llvm/dist/test/Analysis/LoopAccessAnalysis/number-of-memchecks.ll vendor/llvm/dist/test/Analysis/LoopAccessAnalysis/resort-to-memchecks-only.ll vendor/llvm/dist/test/Analysis/LoopAccessAnalysis/unsafe-and-rt-checks.ll vendor/llvm/dist/test/Assembler/getelementptr_vec_idx1.ll vendor/llvm/dist/test/Assembler/getelementptr_vec_idx2.ll vendor/llvm/dist/test/Assembler/getelementptr_vec_idx3.ll vendor/llvm/dist/test/Bitcode/attributes.ll vendor/llvm/dist/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll vendor/llvm/dist/test/CodeGen/AArch64/arm64-shrink-wrapping.ll vendor/llvm/dist/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll vendor/llvm/dist/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll vendor/llvm/dist/test/CodeGen/AMDGPU/ds_read2.ll vendor/llvm/dist/test/CodeGen/AMDGPU/ds_read2_offset_order.ll vendor/llvm/dist/test/CodeGen/AMDGPU/ds_read2st64.ll vendor/llvm/dist/test/CodeGen/AMDGPU/ds_write2.ll vendor/llvm/dist/test/CodeGen/AMDGPU/ds_write2st64.ll vendor/llvm/dist/test/CodeGen/AMDGPU/fmuladd.ll vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.amdgpu.lrp.ll vendor/llvm/dist/test/CodeGen/AMDGPU/llvm.round.ll vendor/llvm/dist/test/CodeGen/AMDGPU/mad-combine.ll vendor/llvm/dist/test/CodeGen/AMDGPU/mad-sub.ll vendor/llvm/dist/test/CodeGen/AMDGPU/madak.ll vendor/llvm/dist/test/CodeGen/AMDGPU/madmk.ll vendor/llvm/dist/test/CodeGen/AMDGPU/mul_uint24.ll vendor/llvm/dist/test/CodeGen/AMDGPU/select-vectors.ll vendor/llvm/dist/test/CodeGen/AMDGPU/select64.ll vendor/llvm/dist/test/CodeGen/AMDGPU/shl.ll vendor/llvm/dist/test/CodeGen/AMDGPU/sint_to_fp.f64.ll vendor/llvm/dist/test/CodeGen/AMDGPU/srl.ll vendor/llvm/dist/test/CodeGen/AMDGPU/uint_to_fp.f64.ll vendor/llvm/dist/test/CodeGen/AMDGPU/vselect.ll vendor/llvm/dist/test/CodeGen/AMDGPU/xor.ll vendor/llvm/dist/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll vendor/llvm/dist/test/CodeGen/ARM/2013-05-13-AAPCS-byval-padding2.ll vendor/llvm/dist/test/CodeGen/ARM/Windows/hard-float.ll vendor/llvm/dist/test/CodeGen/ARM/Windows/long-calls.ll vendor/llvm/dist/test/CodeGen/ARM/Windows/no-arm-mode.ll vendor/llvm/dist/test/CodeGen/ARM/Windows/pic.ll vendor/llvm/dist/test/CodeGen/ARM/Windows/structors.ll vendor/llvm/dist/test/CodeGen/ARM/arm-returnaddr.ll vendor/llvm/dist/test/CodeGen/ARM/byval-align.ll vendor/llvm/dist/test/CodeGen/ARM/fast-isel-call.ll vendor/llvm/dist/test/CodeGen/ARM/fast-isel-intrinsic.ll vendor/llvm/dist/test/CodeGen/ARM/fast-isel-static.ll vendor/llvm/dist/test/CodeGen/ARM/ldrd.ll vendor/llvm/dist/test/CodeGen/ARM/memset-inline.ll vendor/llvm/dist/test/CodeGen/ARM/wrong-t2stmia-size-opt.ll vendor/llvm/dist/test/CodeGen/Hexagon/fusedandshift.ll vendor/llvm/dist/test/CodeGen/MIR/X86/expected-number-after-bb.mir vendor/llvm/dist/test/CodeGen/MIR/X86/global-value-operands.mir vendor/llvm/dist/test/CodeGen/MIR/X86/large-index-number-error.mir vendor/llvm/dist/test/CodeGen/MIR/X86/machine-basic-block-operands.mir vendor/llvm/dist/test/CodeGen/MIR/X86/machine-instructions.mir vendor/llvm/dist/test/CodeGen/MIR/X86/named-registers.mir vendor/llvm/dist/test/CodeGen/MIR/X86/register-mask-operands.mir vendor/llvm/dist/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir vendor/llvm/dist/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir vendor/llvm/dist/test/CodeGen/MIR/llvmIR.mir vendor/llvm/dist/test/CodeGen/MIR/llvmIRMissing.mir vendor/llvm/dist/test/CodeGen/MIR/machine-basic-block-unknown-name.mir vendor/llvm/dist/test/CodeGen/MIR/machine-function-missing-function.mir vendor/llvm/dist/test/CodeGen/MIR/machine-function-missing-name.mir vendor/llvm/dist/test/CodeGen/MIR/machine-function.mir vendor/llvm/dist/test/CodeGen/MIR/register-info.mir vendor/llvm/dist/test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll vendor/llvm/dist/test/CodeGen/PowerPC/ppc-crbits-onoff.ll vendor/llvm/dist/test/CodeGen/PowerPC/ppc64-anyregcc.ll vendor/llvm/dist/test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll vendor/llvm/dist/test/CodeGen/PowerPC/ppc64-fastcc.ll vendor/llvm/dist/test/CodeGen/PowerPC/ppc64-patchpoint.ll vendor/llvm/dist/test/CodeGen/PowerPC/ppc64-stackmap.ll vendor/llvm/dist/test/CodeGen/PowerPC/recipest.ll vendor/llvm/dist/test/CodeGen/PowerPC/sjlj.ll vendor/llvm/dist/test/CodeGen/PowerPC/swaps-le-3.ll vendor/llvm/dist/test/CodeGen/PowerPC/tls-store2.ll vendor/llvm/dist/test/CodeGen/PowerPC/vsx-elementary-arith.ll vendor/llvm/dist/test/CodeGen/PowerPC/vsx-fma-m.ll vendor/llvm/dist/test/CodeGen/PowerPC/vsx-fma-sp.ll vendor/llvm/dist/test/CodeGen/SPARC/basictest.ll vendor/llvm/dist/test/CodeGen/Thumb2/aapcs.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-alloca-sink.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-catch-and-throw.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-catch-scalar.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-catch-unwind.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-frame-vars.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-inalloca.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-min-unwind.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-mixed-catch-and-cleanup.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-multi-catch.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-nested-1.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-nested-2.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-nested-3.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-nested-rethrow.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-nonalloca-frame-values.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-prepared-catch-reordered.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-prepared-catch.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-prepared-cleanups.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-shared-empty-catch.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-similar-catch-blocks.ll vendor/llvm/dist/test/CodeGen/WinEH/cppeh-state-calc-1.ll vendor/llvm/dist/test/CodeGen/WinEH/seh-inlined-finally.ll vendor/llvm/dist/test/CodeGen/WinEH/seh-outlined-finally.ll vendor/llvm/dist/test/CodeGen/WinEH/seh-prepared-basic.ll vendor/llvm/dist/test/CodeGen/WinEH/seh-simple.ll vendor/llvm/dist/test/CodeGen/X86/avx-vperm2x128.ll vendor/llvm/dist/test/CodeGen/X86/avx512-intrinsics.ll vendor/llvm/dist/test/CodeGen/X86/avx512bw-intrinsics.ll vendor/llvm/dist/test/CodeGen/X86/avx512bwvl-intrinsics.ll vendor/llvm/dist/test/CodeGen/X86/fdiv-combine.ll vendor/llvm/dist/test/CodeGen/X86/frameescape.ll vendor/llvm/dist/test/CodeGen/X86/implicit-null-check-negative.ll vendor/llvm/dist/test/CodeGen/X86/implicit-null-check.ll vendor/llvm/dist/test/CodeGen/X86/machine-combiner.ll vendor/llvm/dist/test/CodeGen/X86/pr13577.ll vendor/llvm/dist/test/CodeGen/X86/seh-catch-all-win32.ll vendor/llvm/dist/test/CodeGen/X86/seh-except-finally.ll vendor/llvm/dist/test/CodeGen/X86/sqrt-fastmath.ll vendor/llvm/dist/test/CodeGen/X86/sse2-vector-shifts.ll vendor/llvm/dist/test/CodeGen/X86/sse3.ll vendor/llvm/dist/test/CodeGen/X86/stack-folding-fp-avx1.ll vendor/llvm/dist/test/CodeGen/X86/stack-folding-fp-sse42.ll vendor/llvm/dist/test/CodeGen/X86/vec_fp_to_int.ll vendor/llvm/dist/test/CodeGen/X86/vec_int_to_fp.ll vendor/llvm/dist/test/CodeGen/X86/vector-gep.ll vendor/llvm/dist/test/CodeGen/X86/vector-sext.ll vendor/llvm/dist/test/CodeGen/X86/vector-shift-ashr-128.ll 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vendor/llvm/dist/test/ExecutionEngine/RuntimeDyld/Mips/ELF_O32_PIC_relocations.s vendor/llvm/dist/test/ExecutionEngine/RuntimeDyld/X86/MachO_i386_DynNoPIC_relocations.s vendor/llvm/dist/test/ExecutionEngine/RuntimeDyld/X86/MachO_x86-64_PIC_relocations.s vendor/llvm/dist/test/MC/AArch64/basic-a64-instructions.s vendor/llvm/dist/test/MC/ARM/basic-thumb2-instructions.s vendor/llvm/dist/test/MC/ARM/thumb2-narrow-dp.ll vendor/llvm/dist/test/MC/ARM/thumb_rewrites.s vendor/llvm/dist/test/MC/ELF/relax-arith.s vendor/llvm/dist/test/MC/ELF/relax-arith2.s vendor/llvm/dist/test/MC/Mips/micromips-expansions.s vendor/llvm/dist/test/MC/Mips/mips-expansions-bad.s vendor/llvm/dist/test/MC/Mips/mips-expansions.s vendor/llvm/dist/test/MC/Mips/mips64-expansions.s vendor/llvm/dist/test/MC/Sparc/sparc-alu-instructions.s vendor/llvm/dist/test/MC/Sparc/sparc-mem-instructions.s vendor/llvm/dist/test/MC/Sparc/sparc-synthetic-instructions.s vendor/llvm/dist/test/MC/X86/AlignedBundling/nesting.s vendor/llvm/dist/test/MC/X86/avx512-encodings.s vendor/llvm/dist/test/MC/X86/x86-64-avx512bw.s vendor/llvm/dist/test/MC/X86/x86-64-avx512bw_vl.s vendor/llvm/dist/test/MC/X86/x86-64-avx512dq.s vendor/llvm/dist/test/MC/X86/x86-64-avx512dq_vl.s vendor/llvm/dist/test/MC/X86/x86-64-avx512f_vl.s vendor/llvm/dist/test/MC/X86/x86_errors.s vendor/llvm/dist/test/Object/Mips/elf-mips64-rel.yaml vendor/llvm/dist/test/Object/X86/nm-print-size.s vendor/llvm/dist/test/Object/archive-format.test vendor/llvm/dist/test/Object/archive-symtab.test vendor/llvm/dist/test/Object/archive-toc.test vendor/llvm/dist/test/Object/archive-update.test vendor/llvm/dist/test/Object/coff-archive.test vendor/llvm/dist/test/Object/obj2yaml.test vendor/llvm/dist/test/Object/yaml2obj-elf-rel-noref.yaml vendor/llvm/dist/test/Object/yaml2obj-elf-rel.yaml vendor/llvm/dist/test/Object/yaml2obj-elf-section-basic.yaml vendor/llvm/dist/test/Object/yaml2obj-elf-symbol-basic.yaml vendor/llvm/dist/test/Other/extract.ll vendor/llvm/dist/test/Transforms/Inline/frameescape.ll vendor/llvm/dist/test/Transforms/InstCombine/align-external.ll vendor/llvm/dist/test/Transforms/InstCombine/intrinsics.ll vendor/llvm/dist/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll vendor/llvm/dist/test/Transforms/InstSimplify/floating-point-compare.ll vendor/llvm/dist/test/Transforms/InstSimplify/undef.ll vendor/llvm/dist/test/Transforms/LoopDistribute/basic-with-memchecks.ll vendor/llvm/dist/test/Transforms/LoopUnroll/unroll-pragmas.ll vendor/llvm/dist/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll vendor/llvm/dist/test/Transforms/PlaceSafepoints/statepoint-frameescape.ll vendor/llvm/dist/test/Transforms/SLPVectorizer/AMDGPU/simplebb.ll vendor/llvm/dist/test/Transforms/SLPVectorizer/X86/cse.ll vendor/llvm/dist/test/Transforms/SLPVectorizer/X86/gep.ll vendor/llvm/dist/test/Transforms/SLPVectorizer/X86/loopinvariant.ll vendor/llvm/dist/test/Transforms/SLPVectorizer/X86/pr19657.ll vendor/llvm/dist/test/Transforms/SROA/basictest.ll vendor/llvm/dist/test/Verifier/frameescape.ll vendor/llvm/dist/test/tools/llvm-objdump/macho-sections.test vendor/llvm/dist/test/tools/llvm-readobj/codeview-linetables.test vendor/llvm/dist/tools/dsymutil/DebugMap.cpp vendor/llvm/dist/tools/dsymutil/MachODebugMapParser.cpp vendor/llvm/dist/tools/llc/llc.cpp vendor/llvm/dist/tools/llvm-ar/llvm-ar.cpp vendor/llvm/dist/tools/llvm-cxxdump/llvm-cxxdump.cpp vendor/llvm/dist/tools/llvm-jitlistener/CMakeLists.txt vendor/llvm/dist/tools/llvm-nm/llvm-nm.cpp vendor/llvm/dist/tools/llvm-objdump/COFFDump.cpp vendor/llvm/dist/tools/llvm-objdump/MachODump.cpp vendor/llvm/dist/tools/llvm-objdump/llvm-objdump.cpp vendor/llvm/dist/tools/llvm-objdump/llvm-objdump.h vendor/llvm/dist/tools/llvm-readobj/ARMWinEHPrinter.cpp vendor/llvm/dist/tools/llvm-readobj/COFFDumper.cpp vendor/llvm/dist/tools/llvm-readobj/ELFDumper.cpp vendor/llvm/dist/tools/llvm-readobj/ObjDumper.h vendor/llvm/dist/tools/llvm-readobj/StreamWriter.h vendor/llvm/dist/tools/llvm-readobj/Win64EHDumper.cpp vendor/llvm/dist/tools/llvm-readobj/llvm-readobj.cpp vendor/llvm/dist/tools/llvm-rtdyld/llvm-rtdyld.cpp vendor/llvm/dist/tools/llvm-shlib/CMakeLists.txt vendor/llvm/dist/tools/llvm-stress/llvm-stress.cpp vendor/llvm/dist/tools/llvm-symbolizer/LLVMSymbolize.cpp vendor/llvm/dist/tools/obj2yaml/elf2yaml.cpp vendor/llvm/dist/tools/opt/opt.cpp vendor/llvm/dist/tools/yaml2obj/yaml2elf.cpp vendor/llvm/dist/unittests/ADT/TripleTest.cpp vendor/llvm/dist/unittests/ExecutionEngine/MCJIT/MCJITTest.cpp vendor/llvm/dist/unittests/IR/IRBuilderTest.cpp vendor/llvm/dist/utils/TableGen/CodeGenTarget.cpp vendor/llvm/dist/utils/TableGen/FixedLenDecoderEmitter.cpp vendor/llvm/dist/utils/TableGen/RegisterInfoEmitter.cpp vendor/llvm/dist/utils/TableGen/SubtargetEmitter.cpp vendor/llvm/dist/utils/TableGen/X86DisassemblerTables.cpp vendor/llvm/dist/utils/release/test-release.sh vendor/llvm/dist/utils/unittest/UnitTestMain/TestMain.cpp Modified: vendor/llvm/dist/.gitignore ============================================================================== --- vendor/llvm/dist/.gitignore Fri Aug 7 21:54:38 2015 (r286424) +++ vendor/llvm/dist/.gitignore Fri Aug 7 23:01:33 2015 (r286425) @@ -43,7 +43,9 @@ autoconf/autom4te.cache # Directories to ignore (do not add trailing '/'s, they skip symlinks). #==============================================================================# # External projects that are tracked independently. -projects/*/ +projects/* +!projects/*.* +!projects/Makefile # Clang, which is tracked independently. tools/clang # LLDB, which is tracked independently. Modified: vendor/llvm/dist/autoconf/config.guess ============================================================================== --- vendor/llvm/dist/autoconf/config.guess Fri Aug 7 21:54:38 2015 (r286424) +++ vendor/llvm/dist/autoconf/config.guess Fri Aug 7 23:01:33 2015 (r286425) @@ -810,6 +810,9 @@ EOF *:MINGW*:*) echo ${UNAME_MACHINE}-pc-mingw32 exit ;; + *:MSYS*:*) + echo ${UNAME_MACHINE}-pc-msys + exit ;; i*:windows32*:*) # uname -m includes "-pc" on this system. echo ${UNAME_MACHINE}-mingw32 Modified: vendor/llvm/dist/bindings/python/llvm/object.py ============================================================================== --- vendor/llvm/dist/bindings/python/llvm/object.py Fri Aug 7 21:54:38 2015 (r286424) +++ vendor/llvm/dist/bindings/python/llvm/object.py Fri Aug 7 23:01:33 2015 (r286425) @@ -372,14 +372,6 @@ class Relocation(LLVMObject): self.expired = False @CachedProperty - def address(self): - """The address of this relocation, in long bytes.""" - if self.expired: - raise Exception('Relocation instance has expired.') - - return lib.LLVMGetRelocationAddress(self) - - @CachedProperty def offset(self): """The offset of this relocation, in long bytes.""" if self.expired: @@ -498,9 +490,6 @@ def register_library(library): library.LLVMGetSymbolSize.argtypes = [Symbol] library.LLVMGetSymbolSize.restype = c_uint64 - library.LLVMGetRelocationAddress.argtypes = [c_object_p] - library.LLVMGetRelocationAddress.restype = c_uint64 - library.LLVMGetRelocationOffset.argtypes = [c_object_p] library.LLVMGetRelocationOffset.restype = c_uint64 Modified: vendor/llvm/dist/cmake/modules/AddLLVM.cmake ============================================================================== --- vendor/llvm/dist/cmake/modules/AddLLVM.cmake Fri Aug 7 21:54:38 2015 (r286424) +++ vendor/llvm/dist/cmake/modules/AddLLVM.cmake Fri Aug 7 23:01:33 2015 (r286425) @@ -93,20 +93,9 @@ function(add_llvm_symbol_exports target_ else() set(native_export_file "${target_name}.def") - set(CAT "cat") - set(export_file_nativeslashes ${export_file}) - if(WIN32 AND NOT CYGWIN AND NOT MSYS) - set(CAT "type") - # Convert ${export_file} to native format (backslashes) for "type" - # Does not use file(TO_NATIVE_PATH) as it doesn't create a native - # path but a build-system specific format (see CMake bug - # http://public.kitware.com/Bug/print_bug_page.php?bug_id=5939 ) - string(REPLACE / \\ export_file_nativeslashes ${export_file}) - endif() - add_custom_command(OUTPUT ${native_export_file} - COMMAND ${CMAKE_COMMAND} -E echo "EXPORTS" > ${native_export_file} - COMMAND ${CAT} ${export_file_nativeslashes} >> ${native_export_file} + COMMAND ${PYTHON_EXECUTABLE} -c "import sys;print(''.join(['EXPORTS\\n']+sys.stdin.readlines(),))" + < ${export_file} > ${native_export_file} DEPENDS ${export_file} VERBATIM COMMENT "Creating export file for ${target_name}") @@ -700,10 +689,18 @@ macro(add_llvm_external_project name) list(APPEND LLVM_IMPLICIT_PROJECT_IGNORE "${CMAKE_CURRENT_SOURCE_DIR}/${add_llvm_external_dir}") string(REPLACE "-" "_" nameUNDERSCORE ${name}) string(TOUPPER ${nameUNDERSCORE} nameUPPER) - set(LLVM_EXTERNAL_${nameUPPER}_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/${add_llvm_external_dir}" - CACHE PATH "Path to ${name} source directory") - if (NOT ${LLVM_EXTERNAL_${nameUPPER}_SOURCE_DIR} STREQUAL "" - AND EXISTS ${LLVM_EXTERNAL_${nameUPPER}_SOURCE_DIR}/CMakeLists.txt) + #TODO: Remove this check in a few days once it has circulated through + # buildbots and people's checkouts (cbieneman - July 14, 2015) + if("${LLVM_EXTERNAL_${nameUPPER}_SOURCE_DIR}" STREQUAL "${CMAKE_CURRENT_SOURCE_DIR}/${add_llvm_external_dir}") + unset(LLVM_EXTERNAL_${nameUPPER}_SOURCE_DIR CACHE) + endif() + if(NOT LLVM_EXTERNAL_${nameUPPER}_SOURCE_DIR) + set(LLVM_EXTERNAL_${nameUPPER}_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/${add_llvm_external_dir}") + else() + set(LLVM_EXTERNAL_${nameUPPER}_SOURCE_DIR + CACHE PATH "Path to ${name} source directory") + endif() + if (EXISTS ${LLVM_EXTERNAL_${nameUPPER}_SOURCE_DIR}/CMakeLists.txt) option(LLVM_EXTERNAL_${nameUPPER}_BUILD "Whether to build ${name} as part of LLVM" ON) if (LLVM_EXTERNAL_${nameUPPER}_BUILD) Modified: vendor/llvm/dist/docs/ExceptionHandling.rst ============================================================================== --- vendor/llvm/dist/docs/ExceptionHandling.rst Fri Aug 7 21:54:38 2015 (r286424) +++ vendor/llvm/dist/docs/ExceptionHandling.rst Fri Aug 7 23:01:33 2015 (r286425) @@ -339,11 +339,11 @@ original context before code generation. Catch handlers are called with a pointer to the handler itself as the first argument and a pointer to the parent function's stack frame as the second -argument. The catch handler uses the `llvm.recoverframe -<LangRef.html#llvm-frameallocate-and-llvm-framerecover-intrinsics>`_ to get a +argument. The catch handler uses the `llvm.localrecover +<LangRef.html#llvm-localescape-and-llvm-localrecover-intrinsics>`_ to get a pointer to a frame allocation block that is created in the parent frame using -the `llvm.allocateframe -<LangRef.html#llvm-frameallocate-and-llvm-framerecover-intrinsics>`_ intrinsic. +the `llvm.localescape +<LangRef.html#llvm-localescape-and-llvm-localrecover-intrinsics>`_ intrinsic. The ``WinEHPrepare`` pass will have created a structure definition for the contents of this block. The first two members of the structure will always be (1) a 32-bit integer that the runtime uses to track the exception state of the @@ -520,12 +520,12 @@ action. A code of ``i32 1`` indicates a catch action, which expects three additional arguments. Different EH schemes give different meanings to the three arguments, but the first argument indicates whether the catch should fire, the second is -the frameescape index of the exception object, and the third is the code to run +the localescape index of the exception object, and the third is the code to run to catch the exception. For Windows C++ exception handling, the first argument for a catch handler is a pointer to the RTTI type descriptor for the object to catch. The second -argument is an index into the argument list of the ``llvm.frameescape`` call in +argument is an index into the argument list of the ``llvm.localescape`` call in the main function. The exception object will be copied into the provided stack object. If the exception object is not required, this argument should be -1. The third argument is a pointer to a function implementing the catch. This Modified: vendor/llvm/dist/docs/LangRef.rst ============================================================================== --- vendor/llvm/dist/docs/LangRef.rst Fri Aug 7 21:54:38 2015 (r286424) +++ vendor/llvm/dist/docs/LangRef.rst Fri Aug 7 23:01:33 2015 (r286425) @@ -1326,6 +1326,14 @@ example: On an argument, this attribute indicates that the function does not write through this pointer argument, even though it may write to the memory that the pointer points to. +``argmemonly`` + This attribute indicates that the only memory accesses inside function are + loads and stores from objects pointed to by its pointer-typed arguments, + with arbitrary offsets. Or in other words, all memory operations in the + function can refer to memory only using pointers based on its function + arguments. + Note that ``argmemonly`` can be used together with ``readonly`` attribute + in order to specify that function reads only from its arguments. ``returns_twice`` This attribute indicates that this function can return twice. The C ``setjmp`` is an example of such a function. The compiler disables @@ -1446,8 +1454,8 @@ The strings can contain any character by characters. The escape sequence used is simply "\\xx" where "xx" is the two digit hex code for the number. -The inline asm code is simply printed to the machine code .s file when -assembly code is generated. +Note that the assembly string *must* be parseable by LLVM's integrated assembler +(unless it is disabled), even when emitting a ``.s`` file. .. _langref_datalayout: @@ -1837,8 +1845,8 @@ Fast-Math Flags LLVM IR floating-point binary ops (:ref:`fadd <i_fadd>`, :ref:`fsub <i_fsub>`, :ref:`fmul <i_fmul>`, :ref:`fdiv <i_fdiv>`, -:ref:`frem <i_frem>`) have the following flags that can be set to enable -otherwise unsafe floating point operations +:ref:`frem <i_frem>`, :ref:`fcmp <i_fcmp>`) have the following flags that can +be set to enable otherwise unsafe floating point operations ``nnan`` No NaNs - Allow optimizations to assume the arguments and result are not @@ -2800,13 +2808,36 @@ Inline Assembler Expressions ---------------------------- LLVM supports inline assembler expressions (as opposed to :ref:`Module-Level -Inline Assembly <moduleasm>`) through the use of a special value. This -value represents the inline assembler as a string (containing the -instructions to emit), a list of operand constraints (stored as a -string), a flag that indicates whether or not the inline asm expression -has side effects, and a flag indicating whether the function containing -the asm needs to align its stack conservatively. An example inline -assembler expression is: +Inline Assembly <moduleasm>`) through the use of a special value. This value +represents the inline assembler as a template string (containing the +instructions to emit), a list of operand constraints (stored as a string), a +flag that indicates whether or not the inline asm expression has side effects, +and a flag indicating whether the function containing the asm needs to align its +stack conservatively. + +The template string supports argument substitution of the operands using "``$``" +followed by a number, to indicate substitution of the given register/memory +location, as specified by the constraint string. "``${NUM:MODIFIER}``" may also +be used, where ``MODIFIER`` is a target-specific annotation for how to print the +operand (See :ref:`inline-asm-modifiers`). + +A literal "``$``" may be included by using "``$$``" in the template. To include +other special characters into the output, the usual "``\XX``" escapes may be +used, just as in other strings. Note that after template substitution, the +resulting assembly string is parsed by LLVM's integrated assembler unless it is +disabled -- even when emitting a ``.s`` file -- and thus must contain assembly +syntax known to LLVM. + +LLVM's support for inline asm is modeled closely on the requirements of Clang's +GCC-compatible inline-asm support. Thus, the feature-set and the constraint and +modifier codes listed here are similar or identical to those in GCC's inline asm +support. However, to be clear, the syntax of the template and constraint strings +described here is *not* the same as the syntax accepted by GCC and Clang, and, +while most constraint letters are passed through as-is by Clang, some get +translated to other codes when converting from the C source to the LLVM +assembly. + +An example inline assembler expression is: .. code-block:: llvm @@ -2852,6 +2883,596 @@ If multiple keywords appear the '``sidee first, the '``alignstack``' keyword second and the '``inteldialect``' keyword last. +Inline Asm Constraint String +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The constraint list is a comma-separated string, each element containing one or +more constraint codes. + +For each element in the constraint list an appropriate register or memory +operand will be chosen, and it will be made available to assembly template +string expansion as ``$0`` for the first constraint in the list, ``$1`` for the +second, etc. + +There are three different types of constraints, which are distinguished by a +prefix symbol in front of the constraint code: Output, Input, and Clobber. The +constraints must always be given in that order: outputs first, then inputs, then +clobbers. They cannot be intermingled. + +There are also three different categories of constraint codes: + +- Register constraint. This is either a register class, or a fixed physical + register. This kind of constraint will allocate a register, and if necessary, + bitcast the argument or result to the appropriate type. +- Memory constraint. This kind of constraint is for use with an instruction + taking a memory operand. Different constraints allow for different addressing + modes used by the target. +- Immediate value constraint. This kind of constraint is for an integer or other + immediate value which can be rendered directly into an instruction. The + various target-specific constraints allow the selection of a value in the + proper range for the instruction you wish to use it with. + +Output constraints +"""""""""""""""""" + +Output constraints are specified by an "``=``" prefix (e.g. "``=r``"). This +indicates that the assembly will write to this operand, and the operand will +then be made available as a return value of the ``asm`` expression. Output +constraints do not consume an argument from the call instruction. (Except, see +below about indirect outputs). + +Normally, it is expected that no output locations are written to by the assembly +expression until *all* of the inputs have been read. As such, LLVM may assign +the same register to an output and an input. If this is not safe (e.g. if the +assembly contains two instructions, where the first writes to one output, and +the second reads an input and writes to a second output), then the "``&``" +modifier must be used (e.g. "``=&r``") to specify that the output is an +"early-clobber" output. Marking an ouput as "early-clobber" ensures that LLVM +will not use the same register for any inputs (other than an input tied to this +output). + +Input constraints +""""""""""""""""" + +Input constraints do not have a prefix -- just the constraint codes. Each input +constraint will consume one argument from the call instruction. It is not +permitted for the asm to write to any input register or memory location (unless +that input is tied to an output). Note also that multiple inputs may all be +assigned to the same register, if LLVM can determine that they necessarily all +contain the same value. + +Instead of providing a Constraint Code, input constraints may also "tie" +themselves to an output constraint, by providing an integer as the constraint +string. Tied inputs still consume an argument from the call instruction, and +take up a position in the asm template numbering as is usual -- they will simply +be constrained to always use the same register as the output they've been tied +to. For example, a constraint string of "``=r,0``" says to assign a register for +output, and use that register as an input as well (it being the 0'th +constraint). + +It is permitted to tie an input to an "early-clobber" output. In that case, no +*other* input may share the same register as the input tied to the early-clobber +(even when the other input has the same value). + +You may only tie an input to an output which has a register constraint, not a +memory constraint. Only a single input may be tied to an output. + +There is also an "interesting" feature which deserves a bit of explanation: if a +register class constraint allocates a register which is too small for the value +type operand provided as input, the input value will be split into multiple +registers, and all of them passed to the inline asm. + +However, this feature is often not as useful as you might think. + +Firstly, the registers are *not* guaranteed to be consecutive. So, on those +architectures that have instructions which operate on multiple consecutive +instructions, this is not an appropriate way to support them. (e.g. the 32-bit +SparcV8 has a 64-bit load, which instruction takes a single 32-bit register. The +hardware then loads into both the named register, and the next register. This +feature of inline asm would not be useful to support that.) + +A few of the targets provide a template string modifier allowing explicit access +to the second register of a two-register operand (e.g. MIPS ``L``, ``M``, and +``D``). On such an architecture, you can actually access the second allocated +register (yet, still, not any subsequent ones). But, in that case, you're still +probably better off simply splitting the value into two separate operands, for +clarity. (e.g. see the description of the ``A`` constraint on X86, which, +despite existing only for use with this feature, is not really a good idea to +use) + +Indirect inputs and outputs +""""""""""""""""""""""""""" + +Indirect output or input constraints can be specified by the "``*``" modifier +(which goes after the "``=``" in case of an output). This indicates that the asm +will write to or read from the contents of an *address* provided as an input +argument. (Note that in this way, indirect outputs act more like an *input* than +an output: just like an input, they consume an argument of the call expression, +rather than producing a return value. An indirect output constraint is an +"output" only in that the asm is expected to write to the contents of the input +memory location, instead of just read from it). + +This is most typically used for memory constraint, e.g. "``=*m``", to pass the +address of a variable as a value. + +It is also possible to use an indirect *register* constraint, but only on output +(e.g. "``=*r``"). This will cause LLVM to allocate a register for an output +value normally, and then, separately emit a store to the address provided as +input, after the provided inline asm. (It's not clear what value this +functionality provides, compared to writing the store explicitly after the asm +statement, and it can only produce worse code, since it bypasses many +optimization passes. I would recommend not using it.) + + +Clobber constraints +""""""""""""""""""" + +A clobber constraint is indicated by a "``~``" prefix. A clobber does not +consume an input operand, nor generate an output. Clobbers cannot use any of the +general constraint code letters -- they may use only explicit register +constraints, e.g. "``~{eax}``". The one exception is that a clobber string of +"``~{memory}``" indicates that the assembly writes to arbitrary undeclared +memory locations -- not only the memory pointed to by a declared indirect +output. + + +Constraint Codes +"""""""""""""""" +After a potential prefix comes constraint code, or codes. + +A Constraint Code is either a single letter (e.g. "``r``"), a "``^``" character +followed by two letters (e.g. "``^wc``"), or "``{``" register-name "``}``" +(e.g. "``{eax}``"). + +The one and two letter constraint codes are typically chosen to be the same as +GCC's constraint codes. + +A single constraint may include one or more than constraint code in it, leaving +it up to LLVM to choose which one to use. This is included mainly for +compatibility with the translation of GCC inline asm coming from clang. + +There are two ways to specify alternatives, and either or both may be used in an +inline asm constraint list: + +1) Append the codes to each other, making a constraint code set. E.g. "``im``" + or "``{eax}m``". This means "choose any of the options in the set". The + choice of constraint is made independently for each constraint in the + constraint list. + +2) Use "``|``" between constraint code sets, creating alternatives. Every + constraint in the constraint list must have the same number of alternative + sets. With this syntax, the same alternative in *all* of the items in the + constraint list will be chosen together. + +Putting those together, you might have a two operand constraint string like +``"rm|r,ri|rm"``. This indicates that if operand 0 is ``r`` or ``m``, then +operand 1 may be one of ``r`` or ``i``. If operand 0 is ``r``, then operand 1 +may be one of ``r`` or ``m``. But, operand 0 and 1 cannot both be of type m. + +However, the use of either of the alternatives features is *NOT* recommended, as +LLVM is not able to make an intelligent choice about which one to use. (At the +point it currently needs to choose, not enough information is available to do so +in a smart way.) Thus, it simply tries to make a choice that's most likely to +compile, not one that will be optimal performance. (e.g., given "``rm``", it'll +always choose to use memory, not registers). And, if given multiple registers, +or multiple register classes, it will simply choose the first one. (In fact, it +doesn't currently even ensure explicitly specified physical registers are +unique, so specifying multiple physical registers as alternatives, like +``{r11}{r12},{r11}{r12}``, will assign r11 to both operands, not at all what was +intended.) + +Supported Constraint Code List +"""""""""""""""""""""""""""""" + +The constraint codes are, in general, expected to behave the same way they do in +GCC. LLVM's support is often implemented on an 'as-needed' basis, to support C +inline asm code which was supported by GCC. A mismatch in behavior between LLVM +and GCC likely indicates a bug in LLVM. + +Some constraint codes are typically supported by all targets: + +- ``r``: A register in the target's general purpose register class. +- ``m``: A memory address operand. It is target-specific what addressing modes + are supported, typical examples are register, or register + register offset, + or register + immediate offset (of some target-specific size). +- ``i``: An integer constant (of target-specific width). Allows either a simple + immediate, or a relocatable value. +- ``n``: An integer constant -- *not* including relocatable values. +- ``s``: An integer constant, but allowing *only* relocatable values. +- ``X``: Allows an operand of any kind, no constraint whatsoever. Typically + useful to pass a label for an asm branch or call. + + .. FIXME: but that surely isn't actually okay to jump out of an asm + block without telling llvm about the control transfer???) + +- ``{register-name}``: Requires exactly the named physical register. + +Other constraints are target-specific: + +AArch64: + +- ``z``: An immediate integer 0. Outputs ``WZR`` or ``XZR``, as appropriate. +- ``I``: An immediate integer valid for an ``ADD`` or ``SUB`` instruction, + i.e. 0 to 4095 with optional shift by 12. +- ``J``: An immediate integer that, when negated, is valid for an ``ADD`` or + ``SUB`` instruction, i.e. -1 to -4095 with optional left shift by 12. +- ``K``: An immediate integer that is valid for the 'bitmask immediate 32' of a + logical instruction like ``AND``, ``EOR``, or ``ORR`` with a 32-bit register. +- ``L``: An immediate integer that is valid for the 'bitmask immediate 64' of a + logical instruction like ``AND``, ``EOR``, or ``ORR`` with a 64-bit register. +- ``M``: An immediate integer for use with the ``MOV`` assembly alias on a + 32-bit register. This is a superset of ``K``: in addition to the bitmask + immediate, also allows immediate integers which can be loaded with a single + ``MOVZ`` or ``MOVL`` instruction. +- ``N``: An immediate integer for use with the ``MOV`` assembly alias on a + 64-bit register. This is a superset of ``L``. +- ``Q``: Memory address operand must be in a single register (no + offsets). (However, LLVM currently does this for the ``m`` constraint as + well.) +- ``r``: A 32 or 64-bit integer register (W* or X*). +- ``w``: A 32, 64, or 128-bit floating-point/SIMD register. +- ``x``: A lower 128-bit floating-point/SIMD register (``V0`` to ``V15``). + +AMDGPU: + +- ``r``: A 32 or 64-bit integer register. +- ``[0-9]v``: The 32-bit VGPR register, number 0-9. +- ``[0-9]s``: The 32-bit SGPR register, number 0-9. + + +All ARM modes: + +- ``Q``, ``Um``, ``Un``, ``Uq``, ``Us``, ``Ut``, ``Uv``, ``Uy``: Memory address + operand. Treated the same as operand ``m``, at the moment. + +ARM and ARM's Thumb2 mode: + +- ``j``: An immediate integer between 0 and 65535 (valid for ``MOVW``) +- ``I``: An immediate integer valid for a data-processing instruction. +- ``J``: An immediate integer between -4095 and 4095. +- ``K``: An immediate integer whose bitwise inverse is valid for a + data-processing instruction. (Can be used with template modifier "``B``" to + print the inverted value). +- ``L``: An immediate integer whose negation is valid for a data-processing + instruction. (Can be used with template modifier "``n``" to print the negated + value). +- ``M``: A power of two or a integer between 0 and 32. +- ``N``: Invalid immediate constraint. +- ``O``: Invalid immediate constraint. +- ``r``: A general-purpose 32-bit integer register (``r0-r15``). +- ``l``: In Thumb2 mode, low 32-bit GPR registers (``r0-r7``). In ARM mode, same + as ``r``. +- ``h``: In Thumb2 mode, a high 32-bit GPR register (``r8-r15``). In ARM mode, + invalid. +- ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``, + ``d0-d31``, or ``q0-q15``. +- ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``, + ``d0-d7``, or ``q0-q3``. +- ``t``: A floating-point/SIMD register, only supports 32-bit values: + ``s0-s31``. + +ARM's Thumb1 mode: + +- ``I``: An immediate integer between 0 and 255. +- ``J``: An immediate integer between -255 and -1. +- ``K``: An immediate integer between 0 and 255, with optional left-shift by + some amount. +- ``L``: An immediate integer between -7 and 7. +- ``M``: An immediate integer which is a multiple of 4 between 0 and 1020. +- ``N``: An immediate integer between 0 and 31. +- ``O``: An immediate integer which is a multiple of 4 between -508 and 508. +- ``r``: A low 32-bit GPR register (``r0-r7``). +- ``l``: A low 32-bit GPR register (``r0-r7``). +- ``h``: A high GPR register (``r0-r7``). +- ``w``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s31``, + ``d0-d31``, or ``q0-q15``. +- ``x``: A 32, 64, or 128-bit floating-point/SIMD register: ``s0-s15``, + ``d0-d7``, or ``q0-q3``. +- ``t``: A floating-point/SIMD register, only supports 32-bit values: + ``s0-s31``. + + +Hexagon: + +- ``o``, ``v``: A memory address operand, treated the same as constraint ``m``, + at the moment. +- ``r``: A 32 or 64-bit register. + +MSP430: + +- ``r``: An 8 or 16-bit register. + +MIPS: + +- ``I``: An immediate signed 16-bit integer. +- ``J``: An immediate integer zero. +- ``K``: An immediate unsigned 16-bit integer. +- ``L``: An immediate 32-bit integer, where the lower 16 bits are 0. +- ``N``: An immediate integer between -65535 and -1. +- ``O``: An immediate signed 15-bit integer. +- ``P``: An immediate integer between 1 and 65535. +- ``m``: A memory address operand. In MIPS-SE mode, allows a base address + register plus 16-bit immediate offset. In MIPS mode, just a base register. +- ``R``: A memory address operand. In MIPS-SE mode, allows a base address + register plus a 9-bit signed offset. In MIPS mode, the same as constraint + ``m``. +- ``ZC``: A memory address operand, suitable for use in a ``pref``, ``ll``, or + ``sc`` instruction on the given subtarget (details vary). +- ``r``, ``d``, ``y``: A 32 or 64-bit GPR register. +- ``f``: A 32 or 64-bit FPU register (``F0-F31``), or a 128-bit MSA register + (``W0-W31``). In the case of MSA registers, it is recommended to use the ``w`` + argument modifier for compatibility with GCC. +- ``c``: A 32-bit or 64-bit GPR register suitable for indirect jump (always + ``25``). +- ``l``: The ``lo`` register, 32 or 64-bit. +- ``x``: Invalid. + +NVPTX: + +- ``b``: A 1-bit integer register. +- ``c`` or ``h``: A 16-bit integer register. +- ``r``: A 32-bit integer register. +- ``l`` or ``N``: A 64-bit integer register. +- ``f``: A 32-bit float register. +- ``d``: A 64-bit float register. + + +PowerPC: + +- ``I``: An immediate signed 16-bit integer. +- ``J``: An immediate unsigned 16-bit integer, shifted left 16 bits. +- ``K``: An immediate unsigned 16-bit integer. +- ``L``: An immediate signed 16-bit integer, shifted left 16 bits. +- ``M``: An immediate integer greater than 31. +- ``N``: An immediate integer that is an exact power of 2. +- ``O``: The immediate integer constant 0. +- ``P``: An immediate integer constant whose negation is a signed 16-bit + constant. +- ``es``, ``o``, ``Q``, ``Z``, ``Zy``: A memory address operand, currently + treated the same as ``m``. +- ``r``: A 32 or 64-bit integer register. +- ``b``: A 32 or 64-bit integer register, excluding ``R0`` (that is: + ``R1-R31``). +- ``f``: A 32 or 64-bit float register (``F0-F31``), or when QPX is enabled, a + 128 or 256-bit QPX register (``Q0-Q31``; aliases the ``F`` registers). +- ``v``: For ``4 x f32`` or ``4 x f64`` types, when QPX is enabled, a + 128 or 256-bit QPX register (``Q0-Q31``), otherwise a 128-bit + altivec vector register (``V0-V31``). + + .. FIXME: is this a bug that v accepts QPX registers? I think this + is supposed to only use the altivec vector registers? + +- ``y``: Condition register (``CR0-CR7``). +- ``wc``: An individual CR bit in a CR register. +- ``wa``, ``wd``, ``wf``: Any 128-bit VSX vector register, from the full VSX + register set (overlapping both the floating-point and vector register files). +- ``ws``: A 32 or 64-bit floating point register, from the full VSX register + set. + +Sparc: + +- ``I``: An immediate 13-bit signed integer. +- ``r``: A 32-bit integer register. + +SystemZ: + +- ``I``: An immediate unsigned 8-bit integer. +- ``J``: An immediate unsigned 12-bit integer. +- ``K``: An immediate signed 16-bit integer. +- ``L``: An immediate signed 20-bit integer. +- ``M``: An immediate integer 0x7fffffff. +- ``Q``, ``R``, ``S``, ``T``: A memory address operand, treated the same as + ``m``, at the moment. +- ``r`` or ``d``: A 32, 64, or 128-bit integer register. +- ``a``: A 32, 64, or 128-bit integer address register (excludes R0, which in an + address context evaluates as zero). +- ``h``: A 32-bit value in the high part of a 64bit data register + (LLVM-specific) +- ``f``: A 32, 64, or 128-bit floating point register. + +X86: + +- ``I``: An immediate integer between 0 and 31. +- ``J``: An immediate integer between 0 and 64. +- ``K``: An immediate signed 8-bit integer. +- ``L``: An immediate integer, 0xff or 0xffff or (in 64-bit mode only) + 0xffffffff. +- ``M``: An immediate integer between 0 and 3. +- ``N``: An immediate unsigned 8-bit integer. +- ``O``: An immediate integer between 0 and 127. +- ``e``: An immediate 32-bit signed integer. +- ``Z``: An immediate 32-bit unsigned integer. +- ``o``, ``v``: Treated the same as ``m``, at the moment. +- ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit + ``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d`` + registers, and on X86-64, it is all of the integer registers. +- ``Q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit + ``h`` integer register. This is the ``a``, ``b``, ``c``, and ``d`` registers. +- ``r`` or ``l``: An 8, 16, 32, or 64-bit integer register. +- ``R``: An 8, 16, 32, or 64-bit "legacy" integer register -- one which has + existed since i386, and can be accessed without the REX prefix. +- ``f``: A 32, 64, or 80-bit '387 FPU stack pseudo-register. +- ``y``: A 64-bit MMX register, if MMX is enabled. +- ``x``: If SSE is enabled: a 32 or 64-bit scalar operand, or 128-bit vector + operand in a SSE register. If AVX is also enabled, can also be a 256-bit + vector operand in an AVX register. If AVX-512 is also enabled, can also be a + 512-bit vector operand in an AVX512 register, Otherwise, an error. +- ``Y``: The same as ``x``, if *SSE2* is enabled, otherwise an error. +- ``A``: Special case: allocates EAX first, then EDX, for a single operand (in + 32-bit mode, a 64-bit integer operand will get split into two registers). It + is not recommended to use this constraint, as in 64-bit mode, the 64-bit + operand will get allocated only to RAX -- if two 32-bit operands are needed, + you're better off splitting it yourself, before passing it to the asm + statement. + +XCore: + +- ``r``: A 32-bit integer register. + + +.. _inline-asm-modifiers: + +Asm template argument modifiers +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +In the asm template string, modifiers can be used on the operand reference, like +"``${0:n}``". + +The modifiers are, in general, expected to behave the same way they do in +GCC. LLVM's support is often implemented on an 'as-needed' basis, to support C +inline asm code which was supported by GCC. A mismatch in behavior between LLVM +and GCC likely indicates a bug in LLVM. + +Target-independent: + +- ``c``: Print an immediate integer constant unadorned, without + the target-specific immediate punctuation (e.g. no ``$`` prefix). +- ``n``: Negate and print immediate integer constant unadorned, without the + target-specific immediate punctuation (e.g. no ``$`` prefix). +- ``l``: Print as an unadorned label, without the target-specific label + punctuation (e.g. no ``$`` prefix). + +AArch64: + +- ``w``: Print a GPR register with a ``w*`` name instead of ``x*`` name. E.g., + instead of ``x30``, print ``w30``. +- ``x``: Print a GPR register with a ``x*`` name. (this is the default, anyhow). +- ``b``, ``h``, ``s``, ``d``, ``q``: Print a floating-point/SIMD register with a + ``b*``, ``h*``, ``s*``, ``d*``, or ``q*`` name, rather than the default of + ``v*``. + +AMDGPU: + +- ``r``: No effect. + +ARM: + +- ``a``: Print an operand as an address (with ``[`` and ``]`` surrounding a + register). +- ``P``: No effect. +- ``q``: No effect. +- ``y``: Print a VFP single-precision register as an indexed double (e.g. print + as ``d4[1]`` instead of ``s9``) +- ``B``: Bitwise invert and print an immediate integer constant without ``#`` + prefix. +- ``L``: Print the low 16-bits of an immediate integer constant. +- ``M``: Print as a register set suitable for ldm/stm. Also prints *all* + register operands subsequent to the specified one (!), so use carefully. +- ``Q``: Print the low-order register of a register-pair, or the low-order + register of a two-register operand. +- ``R``: Print the high-order register of a register-pair, or the high-order + register of a two-register operand. +- ``H``: Print the second register of a register-pair. (On a big-endian system, + ``H`` is equivalent to ``Q``, and on little-endian system, ``H`` is equivalent + to ``R``.) + + .. FIXME: H doesn't currently support printing the second register + of a two-register operand. + +- ``e``: Print the low doubleword register of a NEON quad register. +- ``f``: Print the high doubleword register of a NEON quad register. +- ``m``: Print the base register of a memory operand without the ``[`` and ``]`` + adornment. + +Hexagon: + +- ``L``: Print the second register of a two-register operand. Requires that it + has been allocated consecutively to the first. + + .. FIXME: why is it restricted to consecutive ones? And there's + nothing that ensures that happens, is there? + +- ``I``: Print the letter 'i' if the operand is an integer constant, otherwise + nothing. Used to print 'addi' vs 'add' instructions. + +MSP430: + +No additional modifiers. + +MIPS: + +- ``X``: Print an immediate integer as hexadecimal +- ``x``: Print the low 16 bits of an immediate integer as hexadecimal. +- ``d``: Print an immediate integer as decimal. +- ``m``: Subtract one and print an immediate integer as decimal. +- ``z``: Print $0 if an immediate zero, otherwise print normally. +- ``L``: Print the low-order register of a two-register operand, or prints the + address of the low-order word of a double-word memory operand. + + .. FIXME: L seems to be missing memory operand support. + +- ``M``: Print the high-order register of a two-register operand, or prints the + address of the high-order word of a double-word memory operand. + + .. FIXME: M seems to be missing memory operand support. + +- ``D``: Print the second register of a two-register operand, or prints the + second word of a double-word memory operand. (On a big-endian system, ``D`` is + equivalent to ``L``, and on little-endian system, ``D`` is equivalent to + ``M``.) +- ``w``: No effect. Provided for compatibility with GCC which requires this + modifier in order to print MSA registers (``W0-W31``) with the ``f`` + constraint. + +NVPTX: + +- ``r``: No effect. + +PowerPC: + +- ``L``: Print the second register of a two-register operand. Requires that it + has been allocated consecutively to the first. + + .. FIXME: why is it restricted to consecutive ones? And there's + nothing that ensures that happens, is there? + +- ``I``: Print the letter 'i' if the operand is an integer constant, otherwise + nothing. Used to print 'addi' vs 'add' instructions. +- ``y``: For a memory operand, prints formatter for a two-register X-form + instruction. (Currently always prints ``r0,OPERAND``). +- ``U``: Prints 'u' if the memory operand is an update form, and nothing + otherwise. (NOTE: LLVM does not support update form, so this will currently + always print nothing) +- ``X``: Prints 'x' if the memory operand is an indexed form. (NOTE: LLVM does + not support indexed form, so this will currently always print nothing) + +Sparc: + +- ``r``: No effect. + +SystemZ: + +SystemZ implements only ``n``, and does *not* support any of the other +target-independent modifiers. + +X86: + +- ``c``: Print an unadorned integer or symbol name. (The latter is + target-specific behavior for this typically target-independent modifier). +- ``A``: Print a register name with a '``*``' before it. +- ``b``: Print an 8-bit register name (e.g. ``al``); do nothing on a memory + operand. +- ``h``: Print the upper 8-bit register name (e.g. ``ah``); do nothing on a + memory operand. +- ``w``: Print the 16-bit register name (e.g. ``ax``); do nothing on a memory + operand. +- ``k``: Print the 32-bit register name (e.g. ``eax``); do nothing on a memory + operand. +- ``q``: Print the 64-bit register name (e.g. ``rax``), if 64-bit registers are + available, otherwise the 32-bit register name; do nothing on a memory operand. +- ``n``: Negate and print an unadorned integer, or, for operands other than an + immediate integer (e.g. a relocatable symbol expression), print a '-' before + the operand. (The behavior for relocatable symbol expressions is a + target-specific behavior for this typically target-independent modifier) +- ``H``: Print a memory reference with additional offset +8. +- ``P``: Print a memory reference or operand for use as the argument of a call + instruction. (E.g. omit ``(rip)``, even though it's PC-relative.) + +XCore: + +No additional modifiers. + + Inline Asm Metadata ^^^^^^^^^^^^^^^^^^^ @@ -6108,7 +6729,8 @@ Overview: The '``getelementptr``' instruction is used to get the address of a subelement of an :ref:`aggregate <t_aggregate>` data structure. It performs -address calculation only and does not access memory. +address calculation only and does not access memory. The instruction can also +be used to calculate a vector of such addresses. Arguments: """""""""" @@ -6234,12 +6856,61 @@ Example: ; yields i32*:iptr %iptr = getelementptr [10 x i32], [10 x i32]* @arr, i16 0, i16 0 -In cases where the pointer argument is a vector of pointers, each index -must be a vector with the same number of elements. For example: +Vector of pointers: +""""""""""""""""""" + +The ``getelementptr`` returns a vector of pointers, instead of a single address, +when one or more of its arguments is a vector. In such cases, all vector +arguments should have the same number of elements, and every scalar argument +will be effectively broadcast into a vector during address calculation. .. code-block:: llvm - %A = getelementptr i8, <4 x i8*> %ptrs, <4 x i64> %offsets, + ; All arguments are vectors: + ; A[i] = ptrs[i] + offsets[i]*sizeof(i8) + %A = getelementptr i8, <4 x i8*> %ptrs, <4 x i64> %offsets + + ; Add the same scalar offset to each pointer of a vector: + ; A[i] = ptrs[i] + offset*sizeof(i8) + %A = getelementptr i8, <4 x i8*> %ptrs, i64 %offset + + ; Add distinct offsets to the same pointer: + ; A[i] = ptr + offsets[i]*sizeof(i8) + %A = getelementptr i8, i8* %ptr, <4 x i64> %offsets + + ; In all cases described above the type of the result is <4 x i8*> + +The two following instructions are equivalent: + +.. code-block:: llvm + + getelementptr %struct.ST, <4 x %struct.ST*> %s, <4 x i64> %ind1, + <4 x i32> <i32 2, i32 2, i32 2, i32 2>, + <4 x i32> <i32 1, i32 1, i32 1, i32 1>, + <4 x i32> %ind4, + <4 x i64> <i64 13, i64 13, i64 13, i64 13> + + getelementptr %struct.ST, <4 x %struct.ST*> %s, <4 x i64> %ind1, + i32 2, i32 1, <4 x i32> %ind4, i64 13 + +Let's look at the C code, where the vector version of ``getelementptr`` +makes sense: + +.. code-block:: c + + // Let's assume that we vectorize the following loop: + double *A, B; int *C; + for (int i = 0; i < size; ++i) { + A[i] = B[C[i]]; + } + +.. code-block:: llvm + + ; get pointers for 8 elements from array B + %ptrs = getelementptr double, double* %B, <8 x i32> %C + ; load 8 elements from array B into A + %A = call <8 x double> @llvm.masked.gather.v8f64(<8 x double*> %ptrs, + i32 8, <8 x i1> %mask, <8 x double> %passthru) Conversion Operations --------------------- @@ -6913,7 +7584,7 @@ Syntax: :: - <result> = fcmp <cond> <ty> <op1>, <op2> ; yields i1 or <N x i1>:result + <result> = fcmp [fast-math flags]* <cond> <ty> <op1>, <op2> ; yields i1 or <N x i1>:result Overview: """"""""" @@ -6996,6 +7667,15 @@ always yields an :ref:`i1 <t_integer>` r #. ``uno``: yields ``true`` if either operand is a QNAN. #. ``true``: always yields ``true``, regardless of operands. +The ``fcmp`` instruction can also optionally take any number of +:ref:`fast-math flags <fastmath>`, which are optimization hints to enable +otherwise unsafe floating point optimizations. + +Any set of fast-math flags are legal on an ``fcmp`` instruction, but the +only flags that have any effect on its semantics are those that allow +assumptions to be made about the values of input arguments; namely +``nnan``, ``ninf``, and ``nsz``. See :ref:`fastmath` for more information. + Example: """""""" @@ -7780,7 +8460,7 @@ Note that calling this intrinsic does no other aggressive transformations, so the value returned may not be that of the obvious source-language caller. -'``llvm.frameescape``' and '``llvm.framerecover``' Intrinsics +'``llvm.localescape``' and '``llvm.localrecover``' Intrinsics ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Syntax: @@ -7788,49 +8468,47 @@ Syntax: :: - declare void @llvm.frameescape(...) - declare i8* @llvm.framerecover(i8* %func, i8* %fp, i32 %idx) + declare void @llvm.localescape(...) + declare i8* @llvm.localrecover(i8* %func, i8* %fp, i32 %idx) Overview: """"""""" -The '``llvm.frameescape``' intrinsic escapes offsets of a collection of static -allocas, and the '``llvm.framerecover``' intrinsic applies those offsets to a +The '``llvm.localescape``' intrinsic escapes offsets of a collection of static +allocas, and the '``llvm.localrecover``' intrinsic applies those offsets to a live frame pointer to recover the address of the allocation. The offset is -computed during frame layout of the caller of ``llvm.frameescape``. +computed during frame layout of the caller of ``llvm.localescape``. Arguments: """""""""" -All arguments to '``llvm.frameescape``' must be pointers to static allocas or -casts of static allocas. Each function can only call '``llvm.frameescape``' +All arguments to '``llvm.localescape``' must be pointers to static allocas or +casts of static allocas. Each function can only call '``llvm.localescape``' once, and it can only do so from the entry block. -The ``func`` argument to '``llvm.framerecover``' must be a constant +The ``func`` argument to '``llvm.localrecover``' must be a constant bitcasted pointer to a function defined in the current module. The code generator cannot determine the frame allocation offset of functions defined in other modules. -The ``fp`` argument to '``llvm.framerecover``' must be a frame -pointer of a call frame that is currently live. The return value of -'``llvm.frameaddress``' is one way to produce such a value, but most platforms -also expose the frame pointer through stack unwinding mechanisms. - -The ``idx`` argument to '``llvm.framerecover``' indicates which alloca passed to -'``llvm.frameescape``' to recover. It is zero-indexed. +The ``fp`` argument to '``llvm.localrecover``' must be a frame pointer of a +call frame that is currently live. The return value of '``llvm.localaddress``' +is one way to produce such a value, but various runtimes also expose a suitable +pointer in platform-specific ways. + +The ``idx`` argument to '``llvm.localrecover``' indicates which alloca passed to +'``llvm.localescape``' to recover. It is zero-indexed. Semantics: """""""""" -These intrinsics allow a group of functions to access one stack memory -allocation in an ancestor stack frame. The memory returned from -'``llvm.frameallocate``' may be allocated prior to stack realignment, so the -memory is only aligned to the ABI-required stack alignment. Each function may -only call '``llvm.frameallocate``' one or zero times from the function entry -block. The frame allocation intrinsic inhibits inlining, as any frame -allocations in the inlined function frame are likely to be at a different -offset from the one used by '``llvm.framerecover``' called with the -uninlined function. +These intrinsics allow a group of functions to share access to a set of local +stack allocations of a one parent function. The parent function may call the +'``llvm.localescape``' intrinsic once from the function entry block, and the +child functions can use '``llvm.localrecover``' to access the escaped allocas. +The '``llvm.localescape``' intrinsic blocks inlining, as inlining changes where +the escaped allocas are allocated, which would break attempts to use +'``llvm.localrecover``'. .. _int_read_register: .. _int_write_register: @@ -9532,6 +10210,75 @@ Examples: Specialised Arithmetic Intrinsics --------------------------------- +'``llvm.canonicalize.*``' Intrinsic +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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