Date: Fri, 26 May 2000 14:05:48 +0200 (EET) From: Narvi <narvi@haldjas.folklore.ee> To: Peter Jeremy <peter.jeremy@ALCATEL.COM.AU> Cc: Mike Smith <msmith@FreeBSD.ORG>, Terry Lambert <tlambert@primenet.com>, arch@FreeBSD.ORG Subject: Re: Preemptive kernel on older X86 hardware Message-ID: <Pine.BSF.3.96.1000526113550.95256a-100000@haldjas.folklore.ee> In-Reply-To: <00May26.070036est.115225@border.alcanet.com.au>
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On Fri, 26 May 2000, Peter Jeremy wrote: > On Thu, May 25, 2000 at 11:50:12AM +1000, Terry Lambert wrote: > >What would be the "NOP" overhead on a pipelined instruction cache? > > On a 486, a NOP takes 1 cycle to execute. I suspect it's zero on the > more recent processors. As Terry points out, there's also the fetch > cost - but I-fetches are (effectively) free unless the processor bus > is saturated. > NOP cost is not free on a lot of processors. The OOO processors have more resources than just 'execute' that are contended for. At the very least, it eats up issue slots. When and how they are removed from the instruction stream is a processor specific issue and varies widely. > > I don't think this'd work on > >i386, since the replacement code sequence is larger... > > You just have the larger code as the default and patch the smaller > sequence if appropriate. > > Peter > To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message
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