Date: Wed, 17 Jun 2015 10:42:51 GMT From: pratiksinghal@FreeBSD.org To: svn-soc-all@FreeBSD.org Subject: socsvn commit: r287232 - soc2015/pratiksinghal/cubie-head/sys/arm/allwinner Message-ID: <201506171042.t5HAgpNU017549@socsvn.freebsd.org>
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Author: pratiksinghal Date: Wed Jun 17 10:42:51 2015 New Revision: 287232 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=287232 Log: Removed unnecessary comments, printfs and fixed some style issues Modified: soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_mmc.c Modified: soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_mmc.c ============================================================================== --- soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_mmc.c Wed Jun 17 09:44:02 2015 (r287231) +++ soc2015/pratiksinghal/cubie-head/sys/arm/allwinner/a10_mmc.c Wed Jun 17 10:42:51 2015 (r287232) @@ -61,7 +61,7 @@ #define A10_DMA_BUFF_SIZE 512 #define A10_MMC_DMA_FTRGLEVEL_A20 0x20070008 #define A10_MMC_DMA_FTRGLEVEL_A10 0x00070208 -#define A10_MMC_DMA_MAXLEN 0x1000 +#define A10_MMC_DMA_MAXLEN 0x10000 struct a10_mmc_softc { bus_space_handle_t a10_bsh; @@ -91,8 +91,8 @@ bus_dmamap_t a10_dma_map ; bus_dma_tag_t a10_dma_tag ; int a10_dma_ndesc; - void* a10_dma_desc ; /* Contains the kva of the descriptor which we will pass to DLBA */ - int a10_dma_ops ; /* Which type of operation DMA is performing ? 0:read, 1:write, 2:other */ + void* a10_dma_desc ; + int a10_dma_ops ; bus_dma_tag_t a10_dma_buff_tag ; bus_dmamap_t a10_dma_buff_map ; bus_addr_t a10_dma_buff_addr ; @@ -294,10 +294,8 @@ a10_mmc_prepare_dma(struct a10_mmc_softc* sc) { - //device_printf(sc->a10_dev, "Call to prepare dma\n") ; struct a10_mmc_dma_desc* dma = sc->a10_dma_desc ; struct mmc_command* cmd = sc->a10_req->cmd ; - //device_printf(sc->a10_dev,"sc->a10_req = %p, sc->a10_req->cmd = %p, sc->a10_req->cmd->data = %p, dma = %p\n", sc->a10_req,sc->a10_req->cmd,sc->a10_req->cmd->data,dma) ; int read = (sc->a10_req->cmd->data->flags & MMC_DATA_WRITE) ? 0 : 1 ; bus_addr_t desc_paddr = (sc->a10_dma_cb_arg).addr ; bus_size_t off = 0 ; @@ -307,20 +305,17 @@ //bus_size_t len = (sc->a10_dma_cb_arg).segs[0].ds_len ; bus_size_t len = A10_MMC_DMA_MAXLEN ; rem = min(len,cmd->data->len) ; - device_printf(sc->a10_dev, "%d bytes to be transferred\n", rem) ; uint32_t error = bus_dmamap_load(sc->a10_dma_buff_tag, sc->a10_dma_buff_map, cmd->data->data,rem,a10_dma_buff_cb, &sc->a10_dma_buff_addr,BUS_DMA_NOWAIT) ; - if(error != 0) { + if (error != 0) { device_printf(sc->a10_dev, "DMA transaction failed due to insufficient resources\n") ; return EIO ; } bus_addr_t paddr = sc->a10_dma_buff_addr ; - /* Program all the descriptors in this segment. */ - while(rem > 0) - { - if(desc == sc->a10_dma_ndesc) + while (rem > 0) { + if (desc == sc->a10_dma_ndesc) break ; len = min(sc->a10_dma_xfer_len, rem) ; dma[desc].buff_size = htole32(len) ; @@ -330,11 +325,10 @@ cmd->data->len -= len ; rem -= len ; off += len ; - if(desc == 0) { + if (desc == 0) dma[desc].config |= htole32(A10_MMC_DMA_CONFIG_FD) ; - } - if(cmd->data->len == 0) { + if (cmd->data->len == 0) { dma[desc].config |= htole32(A10_MMC_DMA_CONFIG_LD) ; dma[desc].config |= htole32(A10_MMC_DMA_CONFIG_ER) ; dma[desc].next = 0 ; @@ -353,44 +347,25 @@ bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map, BUS_DMASYNC_PREWRITE) ; - /* Enable DMA and interrupts*/ - //device_printf(sc->a10_dev, "Previous value of gctrl was 0x%08X and new value is 0x%08X\n", A10_MMC_READ_4(sc, A10_MMC_GCTRL), A10_MMC_READ_4(sc,A10_MMC_GCTRL) | A10_MMC_DMA_ENABLE | A10_MMC_INT_ENABLE) ; val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) ; val |= A10_MMC_DMA_ENABLE ; val |= A10_MMC_INT_ENABLE ; A10_MMC_WRITE_4(sc, A10_MMC_GCTRL,val) ; - - /* Reset DMA */ val |= A10_MMC_DMA_RESET ; A10_MMC_WRITE_4(sc, A10_MMC_GCTRL,val) ; - - /* IDMA Soft reset */ A10_MMC_WRITE_4(sc, A10_MMC_DMAC,A10_MMC_IDMAC_SOFT_RST) ; - - /* Enable IDMA with Fix burst */ A10_MMC_WRITE_4(sc, A10_MMC_DMAC,A10_MMC_IDMAC_IDMA_ON | A10_MMC_IDMAC_FIX_BURST) ; - - /* Disable interrupts */ val = A10_MMC_READ_4(sc,A10_MMC_IDIE) ; val &= ~(A10_MMC_IDMAC_RECEIVE_INT | A10_MMC_IDMAC_TRANSMIT_INT) ; A10_MMC_WRITE_4(sc,A10_MMC_IDIE, val) ; - - /* Enable required interrupts */ if(read == 1) val |= A10_MMC_IDMAC_RECEIVE_INT ; else val |= A10_MMC_IDMAC_TRANSMIT_INT ; A10_MMC_WRITE_4(sc, A10_MMC_IDIE,val) ; - - /* Give the starting segment physical address */ A10_MMC_WRITE_4(sc, A10_MMC_DLBA,desc_paddr) ; - - /* Configure the watermark level. */ A10_MMC_WRITE_4(sc, A10_MMC_FTRGL,A10_MMC_DMA_FTRGLEVEL_A10) ; - /* Disable debounce*/ - //A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, A10_MMC_READ_4(sc, A10_MMC_GCTRL) & (~A10_MMC_DEBOUNCE_ENABLE)); - //device_printf(sc->a10_dev, "Completed the prepare function\n") ; return (0) ; } @@ -399,7 +374,7 @@ static int a10_mmc_can_do_dma(struct mmc_request* req) { - if(req->cmd->data->len >= A10_MMC_DMA_MAXLEN) + if(req->cmd->data->len >= A10_MMC_DMA_MAXLEN) return (0) ; else return (1) ; @@ -463,10 +438,10 @@ A10_MMC_CMD_DONE | A10_MMC_INT_ERR_BIT | A10_MMC_DATA_OVER | A10_MMC_AUTOCMD_DONE | A10_MMC_RX_DATA_REQ | A10_MMC_TX_DATA_REQ); - uint32_t temp_val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_INT_ENABLE | A10_MMC_ACCESS_BY_AHB ; - temp_val = temp_val & (~A10_MMC_DMA_ENABLE) ; + uint32_t temp_val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_INT_ENABLE | A10_MMC_ACCESS_BY_AHB ; + temp_val = temp_val & (~A10_MMC_DMA_ENABLE) ; /* Enable interrupts and AHB access. */ - A10_MMC_WRITE_4(sc, A10_MMC_GCTRL,temp_val) ; + A10_MMC_WRITE_4(sc, A10_MMC_GCTRL,temp_val) ; return (0); } @@ -638,13 +613,13 @@ sc->a10_req->cmd->error = MMC_ERR_TIMEOUT ; a10_mmc_req_done(sc) ; A10_MMC_UNLOCK(sc) ; - return ; + return ; } sc->a10_intr |= rint; data = sc->a10_req->cmd->data; - //device_printf(sc->a10_dev, "Data is %p\n", data) ; + //device_printf(sc->a10_dev, "Data is %p\n", data) ; if (data != NULL && (rint & (A10_MMC_DATA_OVER | A10_MMC_RX_DATA_REQ | A10_MMC_TX_DATA_REQ)) != 0) a10_mmc_pio_transfer(sc, data); @@ -654,7 +629,6 @@ A10_MMC_UNLOCK(sc); } -/* Interrupt masking in linux kernel apart from RX/TX is still dubious. */ static int a10_mmc_request(device_t bus, device_t child, struct mmc_request *req) { @@ -705,26 +679,24 @@ A10_MMC_WRITE_4(sc, A10_MMC_BLKSZ, blksz); A10_MMC_WRITE_4(sc, A10_MMC_BCNTR, cmd->data->len); - if((sc->a10_use_dma == 1)&&(a10_mmc_can_do_dma(req))) { + if ((sc->a10_use_dma == 1)&&(a10_mmc_can_do_dma(req))) { uint32_t error = a10_mmc_prepare_dma(sc) ; - if(error == 0) { + if (error == 0) { A10_MMC_WRITE_4(sc, A10_MMC_IMASK, A10_MMC_READ_4(sc, A10_MMC_IMASK) | (A10_MMC_TX_DATA_REQ | A10_MMC_RX_DATA_REQ)) ; } - else { - uint32_t temp_val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_INT_ENABLE | A10_MMC_ACCESS_BY_AHB ; - temp_val = temp_val & (~A10_MMC_DMA_ENABLE) ; - A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, temp_val) ; - device_printf(sc->a10_dev, "Before page faullt (1)\n") ; + else { + uint32_t temp_val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_INT_ENABLE | A10_MMC_ACCESS_BY_AHB ; + temp_val = temp_val & (~A10_MMC_DMA_ENABLE) ; + A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, temp_val) ; device_printf(sc->a10_dev, "Couldn't prepare DMA, using pio instead\n") ; } } else { - uint32_t temp_val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_INT_ENABLE | A10_MMC_ACCESS_BY_AHB ; - temp_val = temp_val & (~A10_MMC_DMA_ENABLE) ; - device_printf(sc->a10_dev, "Before page fault (2)\n") ; - A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, temp_val) ; - device_printf(sc->a10_dev, "Couldn't transfer this data with DMA, using pio instead\n") ; + uint32_t temp_val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_INT_ENABLE | A10_MMC_ACCESS_BY_AHB ; + temp_val = temp_val & (~A10_MMC_DMA_ENABLE) ; + A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, temp_val) ; + device_printf(sc->a10_dev, "Couldn't transfer this data with DMA, using pio instead\n") ; } }
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