Date: Wed, 25 Sep 1996 20:06:25 +0200 (MET DST) From: Stefan Esser <se@zpr.uni-koeln.de> To: Bruce Evans <bde@zeta.org.au> Cc: durian@plutotech.com, freebsd-hackers@freebsd.org Subject: Re: Special Cycles on the PCI bus Message-ID: <199609251806.UAA18578@x14.mi.uni-koeln.de> In-Reply-To: <199609240742.RAA22722@godzilla.zeta.org.au> References: <199609240742.RAA22722@godzilla.zeta.org.au>
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Bruce Evans writes: > >Now's the interresting bit - notice the high bits (0xFC) > >in the write/read address. They can't be intentional. I also find > >it interesting that the accesses to FCA0 are full 32 bit writes. > > > > I/O WRITE ADR=0000FC87 > > D32=06xxxxxx > > I/O READ ADR=0000FC87 > > D32=06xxxxxx > > I/O WRITE ADR=0000FC90 > > D32=xxxxxx00 > > I/O READ ADR=0000FC90 > > D32=xxxxxx00 > No, this seems reasonable. isa/pcibus.c does 32-bit accesses to port > 0xc000 | (device << 8ul). Well, but those are only used for config space accesses, and config space is normally not touched at all, after the PCI probe and attach are complete. But depending on the chip set model, the special cycles may actually be requested by writing into those chip set registers, that are normally used to address config space. I'd need to know more about the system configuration (boot messages and the driver that causes the special cycles) and will then try to understand what's going on ... Regards, STefan
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