Date: Sun, 13 May 2007 19:58:35 GMT From: Bruce M Simpson <bms@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 119786 for review Message-ID: <200705131958.l4DJwZcn053088@repoman.freebsd.org>
next in thread | raw e-mail | index | archive | help
http://perforce.freebsd.org/chv.cgi?CH=119786 Change 119786 by bms@bms_anglepoise on 2007/05/13 19:58:21 misc changes to siba-pci bridge code Affected files ... .. //depot/projects/mips2/src/sys/mips/mips32/sentry5/siba_cc.c#6 edit .. //depot/projects/mips2/src/sys/mips/mips32/sentry5/siba_pcib.c#4 edit .. //depot/projects/mips2/src/sys/mips/mips32/sentry5/siba_pcibvar.h#2 edit Differences ... ==== //depot/projects/mips2/src/sys/mips/mips32/sentry5/siba_cc.c#6 (text+ko) ==== @@ -33,6 +33,8 @@ * GPIO lives here. * The hardware watchdog lives here. * Clock control registers live here. + * You don't need to read them to determine the clock speed on the 5365, + * which is always 200MHz and thus may be hardcoded (for now). * Flash config registers live here. There may or may not be system flash. * The external interface bus lives here (conditionally). * There is a JTAG interface here which may be used to attach probes to ==== //depot/projects/mips2/src/sys/mips/mips32/sentry5/siba_pcib.c#4 (text+ko) ==== @@ -63,12 +63,33 @@ #define MIPS_MEM_RID 0x20 #endif +#define SIBA_PCI_SLOTMAX 16 + +#define siba_pcib_read_4(sc, reg) \ + bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, (reg)) + +#define siba_pcib_write_4(sc, reg, val) \ + bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, (reg), (val)) + +#define SIBA_PCIB_CFG 0x0c000000 /* bottom pci window (64MB) */ + +#define SIBA_PCIB_SBTOPCI0 0x0100 +#define SIBA_PCIB_SBTOPCI1 0x0104 +#define SIBA_PCIB_SBTOPCI2 0x0108 + +#define SIBA_PCIB_SBTOPCICFG0 0x00000002 +#define SIBA_PCIB_SBTOPCICFG1 0x00000003 +#define SIBA_PCIB_SBTOPCICFG0_MASK 0xfc000000 +#define SIBA_PCIB_SBTOPCICFG1_MASK 0xfc000000 +#define SIBA_PCIB_SBTOPCICFG2_MASK 0xc0000000 + /* * TODO: interrupt routing. * TODO: implement configuration space access. * TODO: map pci i/o windows. * TODO: fully implement bus allocation. * TODO: implement resource managers. + * TODO: code cleanup. */ static int siba_pcib_activate_resource(device_t, device_t, int, @@ -79,6 +100,8 @@ static int siba_pcib_attach(device_t); static int siba_pcib_deactivate_resource(device_t, device_t, int, int, struct resource *); +static bus_addr_t + siba_pcib_map_csr(device_t, u_int, u_int, u_int, u_int); static int siba_pcib_maxslots(device_t); static int siba_pcib_probe(device_t); static u_int32_t @@ -100,6 +123,8 @@ siba_pcib_probe(device_t dev) { + /* TODO: support earlier cores. */ + /* TODO: Check if PCI host mode is enabled in the SPROM. */ if (siba_get_vendor(dev) == SIBA_VID_BROADCOM && siba_get_device(dev) == SIBA_DEVID_PCI) { device_set_desc(dev, "SiBa-to-PCI host bridge"); @@ -112,8 +137,7 @@ static int siba_pcib_attach(device_t dev) { - //struct siba_pcib_softc *sc = device_get_softc(dev); - struct resource *mem; + struct siba_pcib_softc *sc = device_get_softc(dev); int rid; /* @@ -121,13 +145,16 @@ * determined for us. */ rid = MIPS_MEM_RID; - mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + sc->sc_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); - if (mem == NULL) { + if (sc->sc_mem == NULL) { device_printf(dev, "unable to allocate memory\n"); return (ENXIO); } + sc->sc_bt = rman_get_bustag(sc->sc_mem); + sc->sc_bh = rman_get_bushandle(sc->sc_mem); + device_add_child(dev, "pci", -1); return (bus_generic_attach(dev)); } @@ -267,7 +294,8 @@ siba_pcib_maxslots(device_t dev) { - //return (PCI_SLOTMAX); + //return (SIBA_PCI_SLOTMAX); + // For now, only probe the first function including the bridge. return (1); } @@ -275,10 +303,31 @@ siba_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) { + bus_addr_t csrbase; + uint32_t val; + + /* + * XXX: TODO de-mipsify; we should map windows for the space + * the bridge uses and do bus_space_read in those as nexus will + * translate accesses into KSEG1 for us. + */ + csrbase = siba_pcib_map_csr(dev, bus, slot, func, reg); + val = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(csrbase); + + switch (bytes) { + case 1: + val &= 0xff; + break; + case 2: + val &= 0xffff; + break; + case 4: + break; + default: + return (ENXIO); + } - /* read from pci configuration space */ - device_printf(dev, "%s: not yet implemented\n", __func__); - return (-1); + return (val); } static void @@ -298,6 +347,43 @@ return (-1); } +/* + * Map CSR registers of a device on the PCI bus into an available window. + * XXX This should really use bus_space_map. + * XXX I need to map these windows before I can use them. + */ +static bus_addr_t +siba_pcib_map_csr(device_t dev, u_int bus, u_int slot, u_int func, u_int reg) +{ + struct siba_pcib_softc *sc = device_get_softc(dev); + bus_addr_t csrbase, csrmap; + + printf("%s: entry", __func__); + (void)sc; + + if (bus == 0) { + csrbase = SIBA_PCIB_SBTOPCICFG0 | + ((1 << (slot + 16)) & SIBA_PCIB_SBTOPCICFG1_MASK); + // XXX exception here + //siba_pcib_write_4(sc, SIBA_PCIB_SBTOPCI0, csrbase); + + csrmap = SIBA_PCIB_CFG | + ((1 << (slot + 16)) & ~SIBA_PCIB_SBTOPCICFG1_MASK) | + (func << 8) | (reg & ~3); + } else { + // XXX exception here + //siba_pcib_write_4(sc, SIBA_PCIB_SBTOPCI0, + // SIBA_PCIB_SBTOPCICFG1); + csrmap = SIBA_PCIB_CFG | (bus << 16) | (slot << 11) | + (func << 8) | (reg & ~3); + } + + printf("%s: %d/%d/%d reg %d mapped at %08x\n", __func__, bus, slot, func, reg, + csrmap); + + return (csrmap); +} + static device_method_t siba_pcib_methods[] = { /* Device interface */ DEVMETHOD(device_attach, siba_pcib_attach), ==== //depot/projects/mips2/src/sys/mips/mips32/sentry5/siba_pcibvar.h#2 (text+ko) ==== @@ -34,9 +34,10 @@ u_int sc_bus; /* PCI bus number */ struct resource *sc_mem; /* siba memory window */ struct resource *sc_csr; /* config space */ -#if 0 + bus_space_tag_t sc_bt; bus_space_handle_t sc_bh; +#if 0 bus_addr_t sc_maddr; bus_size_t sc_msize;
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200705131958.l4DJwZcn053088>