Date: Sun, 7 Jul 2013 19:05:36 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-9@freebsd.org Subject: svn commit: r252993 - in stable/9/contrib/llvm: include/llvm/CodeGen lib/CodeGen lib/CodeGen/SelectionDAG Message-ID: <201307071905.r67J5aqL001660@svn.freebsd.org>
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Author: dim Date: Sun Jul 7 19:05:35 2013 New Revision: 252993 URL: http://svnweb.freebsd.org/changeset/base/252993 Log: MFC r252720: Pull in r185594 from llvm trunk: Add MachineBasicBlock::addLiveIn(). This function adds a live-in physical register to an MBB and ensures that it is copied to a virtual register immediately. Pull in r185615 from llvm trunk: Live-in copies go *after* EH_LABELs. This will soon be tested by exception handling working at all. Pull in r185617 from llvm trunk: Simplify landing pad lowering. Stop using the ISD::EXCEPTIONADDR and ISD::EHSELECTION when lowering landing pad arguments. These nodes were previously legalized into CopyFromReg nodes, but that never worked properly because the CopyFromReg node weren't guaranteed to be scheduled at the top of the basic block. This meant the exception pointer and selector registers could be clobbered before being copied to a virtual register. This patch copies the two physical registers to virtual registers at the beginning of the basic block, and lowers the landingpad instruction directly to two CopyFromReg nodes reading the *virtual* registers. This is safe because virtual registers don't get clobbered. A future patch will remove the ISD::EXCEPTIONADDR and ISD::EHSELECTION nodes. Together, these changes fix llvm PR 16038 ('qt4 webcore file results in "Bad machine code: Using an undefined physical register"'), and should make it possible again to compile the www/qt4-webkit port again on the i386 arch, without using a CPUTYPE=i686 or higher setting. Modified: stable/9/contrib/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h stable/9/contrib/llvm/include/llvm/CodeGen/MachineBasicBlock.h stable/9/contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp stable/9/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp stable/9/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Directory Properties: stable/9/contrib/llvm/ (props changed) Modified: stable/9/contrib/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h ============================================================================== --- stable/9/contrib/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h Sun Jul 7 19:04:10 2013 (r252992) +++ stable/9/contrib/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h Sun Jul 7 19:05:35 2013 (r252993) @@ -115,6 +115,11 @@ public: /// there's no other convenient place for it to live right now. std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate; + /// If the current MBB is a landing pad, the exception pointer and exception + /// selector registers are copied into these virtual registers by + /// SelectionDAGISel::PrepareEHLandingPad(). + unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg; + explicit FunctionLoweringInfo(const TargetLowering &TLI); /// set - Initialize this FunctionLoweringInfo with the given Function Modified: stable/9/contrib/llvm/include/llvm/CodeGen/MachineBasicBlock.h ============================================================================== --- stable/9/contrib/llvm/include/llvm/CodeGen/MachineBasicBlock.h Sun Jul 7 19:04:10 2013 (r252992) +++ stable/9/contrib/llvm/include/llvm/CodeGen/MachineBasicBlock.h Sun Jul 7 19:05:35 2013 (r252993) @@ -296,6 +296,11 @@ public: /// is an error to add the same register to the same set more than once. void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); } + /// Add PhysReg as live in to this block, and ensure that there is a copy of + /// PhysReg to a virtual register of class RC. Return the virtual register + /// that is a copy of the live in PhysReg. + unsigned addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC); + /// removeLiveIn - Remove the specified register from the live in set. /// void removeLiveIn(unsigned Reg); Modified: stable/9/contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp ============================================================================== --- stable/9/contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp Sun Jul 7 19:04:10 2013 (r252992) +++ stable/9/contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp Sun Jul 7 19:05:35 2013 (r252993) @@ -19,6 +19,7 @@ #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SlotIndexes.h" @@ -341,6 +342,38 @@ bool MachineBasicBlock::isLiveIn(unsigne return I != livein_end(); } +unsigned +MachineBasicBlock::addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC) { + assert(getParent() && "MBB must be inserted in function"); + assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg"); + assert(RC && "Register class is required"); + assert((isLandingPad() || this == &getParent()->front()) && + "Only the entry block and landing pads can have physreg live ins"); + + bool LiveIn = isLiveIn(PhysReg); + iterator I = SkipPHIsAndLabels(begin()), E = end(); + MachineRegisterInfo &MRI = getParent()->getRegInfo(); + const TargetInstrInfo &TII = *getParent()->getTarget().getInstrInfo(); + + // Look for an existing copy. + if (LiveIn) + for (;I != E && I->isCopy(); ++I) + if (I->getOperand(1).getReg() == PhysReg) { + unsigned VirtReg = I->getOperand(0).getReg(); + if (!MRI.constrainRegClass(VirtReg, RC)) + llvm_unreachable("Incompatible live-in register class."); + return VirtReg; + } + + // No luck, create a virtual register. + unsigned VirtReg = MRI.createVirtualRegister(RC); + BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg) + .addReg(PhysReg, RegState::Kill); + if (!LiveIn) + addLiveIn(PhysReg); + return VirtReg; +} + void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) { getParent()->splice(NewAfter, this); } Modified: stable/9/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp ============================================================================== --- stable/9/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sun Jul 7 19:04:10 2013 (r252992) +++ stable/9/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sun Jul 7 19:05:35 2013 (r252993) @@ -1910,33 +1910,25 @@ void SelectionDAGBuilder::visitLandingPa SmallVector<EVT, 2> ValueVTs; ComputeValueVTs(TLI, LP.getType(), ValueVTs); + assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported"); - // Insert the EXCEPTIONADDR instruction. - assert(FuncInfo.MBB->isLandingPad() && - "Call to eh.exception not in landing pad!"); - SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); + // Get the two live-in registers as SDValues. The physregs have already been + // copied into virtual registers. SDValue Ops[2]; - Ops[0] = DAG.getRoot(); - SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); - SDValue Chain = Op1.getValue(1); - - // Insert the EHSELECTION instruction. - VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); - Ops[0] = Op1; - Ops[1] = Chain; - SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); - Chain = Op2.getValue(1); - Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); + Ops[0] = DAG.getZExtOrTrunc( + DAG.getCopyFromReg(DAG.getEntryNode(), getCurDebugLoc(), + FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()), + getCurDebugLoc(), ValueVTs[0]); + Ops[1] = DAG.getZExtOrTrunc( + DAG.getCopyFromReg(DAG.getEntryNode(), getCurDebugLoc(), + FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()), + getCurDebugLoc(), ValueVTs[1]); - Ops[0] = Op1; - Ops[1] = Op2; + // Merge into one. SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), DAG.getVTList(&ValueVTs[0], ValueVTs.size()), &Ops[0], 2); - - std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); - setValue(&LP, RetPair.first); - DAG.setRoot(RetPair.second); + setValue(&LP, Res); } /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for Modified: stable/9/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp ============================================================================== --- stable/9/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Jul 7 19:04:10 2013 (r252992) +++ stable/9/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Jul 7 19:05:35 2013 (r252993) @@ -827,12 +827,13 @@ void SelectionDAGISel::PrepareEHLandingP .addSym(Label); // Mark exception register as live in. - unsigned Reg = TLI.getExceptionPointerRegister(); - if (Reg) MBB->addLiveIn(Reg); + const TargetRegisterClass *PtrRC = TLI.getRegClassFor(TLI.getPointerTy()); + if (unsigned Reg = TLI.getExceptionPointerRegister()) + FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC); // Mark exception selector register as live in. - Reg = TLI.getExceptionSelectorRegister(); - if (Reg) MBB->addLiveIn(Reg); + if (unsigned Reg = TLI.getExceptionSelectorRegister()) + FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC); } /// isFoldedOrDeadInstruction - Return true if the specified instruction is @@ -970,6 +971,8 @@ void SelectionDAGISel::SelectAllBasicBlo FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); // Setup an EH landing-pad block. + FuncInfo->ExceptionPointerVirtReg = 0; + FuncInfo->ExceptionSelectorVirtReg = 0; if (FuncInfo->MBB->isLandingPad()) PrepareEHLandingPad();
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