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Date:      Mon, 11 Jul 2016 22:53:23 +0000 (UTC)
From:      Nathan Whitehorn <nwhitehorn@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-projects@freebsd.org
Subject:   svn commit: r302597 - projects/powernv/powerpc/pseries
Message-ID:  <201607112253.u6BMrNvr017462@repo.freebsd.org>
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Author: nwhitehorn
Date: Mon Jul 11 22:53:22 2016
New Revision: 302597
URL: https://svnweb.freebsd.org/changeset/base/302597

Log:
  Fix OPAL XICS CPU assignment: CPU IDs need to be shifted left 2 bits.

Modified:
  projects/powernv/powerpc/pseries/xics.c

Modified: projects/powernv/powerpc/pseries/xics.c
==============================================================================
--- projects/powernv/powerpc/pseries/xics.c	Mon Jul 11 21:55:56 2016	(r302596)
+++ projects/powernv/powerpc/pseries/xics.c	Mon Jul 11 22:53:22 2016	(r302597)
@@ -281,7 +281,7 @@ xicp_bind(device_t dev, u_int irq, cpuse
 		error = rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu,
 		    XICP_PRIORITY, &status);
 	else
-		error = opal_call(OPAL_SET_XIVE, irq, cpu, XICP_PRIORITY);
+		error = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY);
 
 	if (error < 0)
 		panic("Cannot bind interrupt %d to CPU %d", irq, cpu);
@@ -371,8 +371,12 @@ xicp_enable(device_t dev, u_int irq, u_i
 		    XICP_PRIORITY, &status);
 		xicp_unmask(dev, irq);
 	} else {
-		opal_call(OPAL_SET_XIVE, irq, cpu, XICP_PRIORITY);
+		status = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY);
 		/* Unmask implicit for OPAL */
+
+		if (status != 0)
+			panic("OPAL_SET_XIVE IRQ %d -> cpu %d failed: %d", irq,
+			    cpu, status);
 	}
 }
 
@@ -420,7 +424,7 @@ xicp_mask(device_t dev, u_int irq)
 			}
 		}
 		KASSERT(i < sc->nintvecs, ("Masking unconfigured interrupt"));
-		opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu, 0xff);
+		opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu << 2, 0xff);
 	}
 }
 
@@ -443,7 +447,7 @@ xicp_unmask(device_t dev, u_int irq)
 			}
 		}
 		KASSERT(i < sc->nintvecs, ("Unmasking unconfigured interrupt"));
-		opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu,
+		opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu << 2,
 		    XICP_PRIORITY);
 	}
 }

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