Date: Thu, 20 Oct 2005 09:58:07 -0400 From: John Baldwin <jhb@freebsd.org> To: Bruce Evans <bde@zeta.org.au> Cc: Scott Long <scottl@samsco.org>, src-committers@freebsd.org, Andrew Gallatin <gallatin@cs.duke.edu>, cvs-src@freebsd.org, cvs-all@freebsd.org, David Xu <davidxu@freebsd.org> Subject: Re: cvs commit: src/sys/amd64/amd64 cpu_switch.S machdep.c Message-ID: <200510200958.09182.jhb@freebsd.org> In-Reply-To: <20051020145234.H99720@delplex.bde.org> References: <200510172310.j9HNAVPL013057@repoman.freebsd.org> <4355080C.302@samsco.org> <20051020145234.H99720@delplex.bde.org>
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On Thursday 20 October 2005 01:45 am, Bruce Evans wrote: > On Tue, 18 Oct 2005, Scott Long wrote: > I use 100 and never downgraded to use 1000 except for testing how bad > it is. The default number is now up to <number of CPUs> * 2 * HZ. > E.g., it is 4000 on sledge.freebsd.org. While 4000 interrupts/sec can > be handled easily by any new machine, 4000 is a disgustingly large > number to use for clock interrupts. Have a look at vmstat -i output > on almost any machine. On most machines in the freebsd cluster, the > total number of interrupts is dominated by clock interrupts even with > HZ = 100. Note that on 4.x you don't get to see the interrupt counts for the hz + stathz * (cpus - 1) IPIs for all the clock interrupts, so in real numbers, each CPU has gone from hz + stathz to hz * 2 interrupts. However, the higher number is offset by the fact that the interrupt handler for the lapic case doesn't have to touch any hardware, and it also works much more reliably (getting irq0 to work in APIC mode on some amd64 nvidia chipsets required several quirks, and future motherboards will probably continue to require quirks since Windows uses the APIC timer in APIC mode and doesn't require irq0 to work in APIC mode). -- John Baldwin <jhb@FreeBSD.org> <>< http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve" = http://www.FreeBSD.org
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