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Date:      Fri, 24 May 2002 20:06:22 -0400
From:      Paul Murphy <pnmurphy@cogeco.ca>
To:        John Baldwin <jhb@FreeBSD.ORG>
Cc:        current@FreeBSD.ORG
Subject:   Re: Please test PAUSE on non-Intel processors
Message-ID:  <20020524200622.0cce3f96.pnmurphy@cogeco.ca>
In-Reply-To: <XFMail.20020524102553.jhb@FreeBSD.org>
References:  <XFMail.20020524102553.jhb@FreeBSD.org>

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On Fri, 24 May 2002 10:25:53 -0400 (EDT)
John Baldwin <jhb@FreeBSD.ORG> wrote:

> Hey gang, although Intel's document seems to claim that they tested
> proper operation of pause I'd like people with non-Intel processors
> to verify that it actually works.  Please compile the attached test
> program and run it.  The output should look like this:
> 
> > ./pt
> Testing PAUSE instruction:
> Register esp changed: 0xbfbff9fc -> 0xbfbff9c0
> 
> If you get a signal or any of the other registers change their value,
> please let me know.  I've tested this on a Pentium III mobile, a
> K6-II, and an Athlon.  The program cmopiles ok on both stable and
> current.
> 

 CPU: AMD Athlon(tm) Processor (1210.79-MHz 686-class CPU)
  Origin = "AuthenticAMD"  Id = 0x642  Stepping = 2
  Features=0x183f9ff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,SEP,MTRR,PGE,
  MCA,CMOV,PAT,PSE36,MMX,FXSR>
  AMD Features=0xc0440000<<b18>,AMIE,DSP,3DNow!>

[earth] /home/paul/temp: uname -v
FreeBSD 4.5-STABLE #0: Wed Feb 27 03:19:35 EST 2002    
root@earth.upton.net:/usr/obj/usr/src/sys/EARTH

[earth] /home/paul/temp: ./pausetest
Testing PAUSE instruction:
Register esp changed: 0xbfbffa54 -> 0xbfbffa18

-- 
Cogeco ergo sum
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