Date: Tue, 3 Feb 2015 00:12:49 GMT From: John-Mark Gurney <jmg@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 1205651 for review Message-ID: <201502030012.t130Cnni073962@skunkworks.freebsd.org>
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http://p4web.freebsd.org/@@1205651?ac=10 Change 1205651 by jmg@jmg_pciehp on 2015/02/03 00:12:18 Add inital work to make PCIe HotPlug work... This has been tested w/: <inserted ExpressCard> uart3: <MosChip MCS9922 PCIe to Peripheral Controller> port 0x3000-0x3007 at device 0.0 on pci2 uart4: <MosChip MCS9922 PCIe to Peripheral Controller> port 0x3008-0x300f at device 0.1 on pci2 <removed ExpressCard> uart3: detached uart4: detached <inserted ExpressCard> uart3: <MosChip MCS9922 PCIe to Peripheral Controller> port 0x3000-0x3007 at device 0.0 on pci2 uart4: <MosChip MCS9922 PCIe to Peripheral Controller> port 0x3008-0x300f at device 0.1 on pci2 This work is based upon gavin's project branch, but fixed to make some things work.. Right now there is a nasty bit as we don't have a way for a non-acpi driver to add a new PCI device, so the code hard codes the extra space necessary for ACPI... This will be fixed by adding necessary bus functions to tell ACPI to rescan the bus, etc... Sponsored by: FreeBSD Foundation Affected files ... .. //depot/projects/pciehotplug/sys/conf/files#2 edit .. //depot/projects/pciehotplug/sys/dev/pci/pci.c#2 edit .. //depot/projects/pciehotplug/sys/dev/pci/pci_private.h#2 edit .. //depot/projects/pciehotplug/sys/dev/pci/pcie_hp.c#1 add .. //depot/projects/pciehotplug/sys/dev/pci/pcireg.h#2 edit .. //depot/projects/pciehotplug/sys/dev/pci/pcivar.h#2 edit Differences ... ==== //depot/projects/pciehotplug/sys/conf/files#2 (text+ko) ==== @@ -2032,6 +2032,7 @@ dev/pci/pci_user.c optional pci dev/pci/pcib_if.m standard dev/pci/pcib_support.c standard +dev/pci/pcie_hp.c optional pci dev/pci/vga_pci.c optional pci dev/pcn/if_pcn.c optional pcn pci dev/pdq/if_fea.c optional fea eisa ==== //depot/projects/pciehotplug/sys/dev/pci/pci.c#2 (text+ko) ==== @@ -3535,6 +3535,7 @@ void pci_add_child(device_t bus, struct pci_devinfo *dinfo) { + dinfo->cfg.dev = device_add_child(bus, NULL, -1); device_set_ivars(dinfo->cfg.dev, dinfo); resource_list_init(&dinfo->resources); @@ -3605,6 +3606,9 @@ if (!tag_valid) #endif sc->sc_dma_tag = bus_get_dma_tag(dev); + + pci_hotplug_init(dev); + return (0); } ==== //depot/projects/pciehotplug/sys/dev/pci/pci_private.h#2 (text+ko) ==== @@ -140,4 +140,6 @@ */ void pci_cfg_save(device_t, struct pci_devinfo *, int); +void pci_hotplug_init(device_t dev); + #endif /* _PCI_PRIVATE_H_ */ ==== //depot/projects/pciehotplug/sys/dev/pci/pcireg.h#2 (text+ko) ==== @@ -763,6 +763,7 @@ #define PCIEM_SLOT_CAP_EIP 0x00020000 #define PCIEM_SLOT_CAP_NCCS 0x00040000 #define PCIEM_SLOT_CAP_PSN 0xfff80000 +#define PCIEM_SLOT_CAP_GETPSN(x) (((x) & PCIEM_SLOT_CAP_PSN) >> 19) #define PCIER_SLOT_CTL 0x18 #define PCIEM_SLOT_CTL_ABPE 0x0001 #define PCIEM_SLOT_CTL_PFDE 0x0002 @@ -785,6 +786,7 @@ #define PCIEM_SLOT_STA_PDS 0x0040 #define PCIEM_SLOT_STA_EIS 0x0080 #define PCIEM_SLOT_STA_DLLSC 0x0100 +#define PCIEM_SLOT_STA_EMASK 0x011f #define PCIER_ROOT_CTL 0x1c #define PCIEM_ROOT_CTL_SERR_CORR 0x0001 #define PCIEM_ROOT_CTL_SERR_NONFATAL 0x0002 ==== //depot/projects/pciehotplug/sys/dev/pci/pcivar.h#2 (text+ko) ==== @@ -30,7 +30,11 @@ #ifndef _PCIVAR_H_ #define _PCIVAR_H_ +#include <sys/systm.h> +#include <sys/lock.h> +#include <sys/mutex.h> #include <sys/queue.h> +#include <sys/taskqueue.h> /* some PCI bus constants */ #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ @@ -124,6 +128,8 @@ uint64_t ht_msiaddr; /* MSI mapping base address */ }; +#define PCIE_MSI_MESSAGES 2 + /* Interesting values for PCI-express */ struct pcicfg_pcie { uint8_t pcie_location; /* Offset of PCI-e capability registers. */ @@ -136,6 +142,9 @@ uint16_t pcie_device_ctl2; /* Second device control register. */ uint16_t pcie_link_ctl2; /* Second link control register. */ uint16_t pcie_slot_ctl2; /* Second slot control register. */ + struct resource_spec *pcie_irq_spec; + struct resource *pcie_res_irq[PCIE_MSI_MESSAGES]; + void *pcie_intrhand[PCIE_MSI_MESSAGES]; }; struct pcicfg_pcix { @@ -143,6 +152,14 @@ uint8_t pcix_location; /* Offset of PCI-X capability registers. */ }; +/* Interesting values for PCIe Hotplug */ +struct pcicfg_hp { + struct task hp_inttask; + struct callout_handle hp_dllhndl; + int hp_cnt; /* Giant locked */ + uint32_t hp_slotcap; /* cache this */ +}; + /* config header information common to all header types */ typedef struct pcicfg { struct device *dev; /* device which owns this */ @@ -186,6 +203,7 @@ struct pcicfg_ht ht; /* HyperTransport */ struct pcicfg_pcie pcie; /* PCI Express */ struct pcicfg_pcix pcix; /* PCI-X */ + struct pcicfg_hp hp; /* Hotplug */ } pcicfgregs; /* additional type 1 device config header information (PCI to PCI bridge) */
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