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Date:      Mon, 2 Jul 2001 13:32:26 -0700 (PDT)
From:      seanj <seanj@speakeasy.org>
To:        Julian Elischer <julian@elischer.org>
Cc:        Alfred Perlstein <bright@sneakerz.org>, "Michael C . Wu" <keichii@peorth.iteration.net>, "E.B. Dreger" <eddy+public+spam@noc.everquick.net>, "smp@FreeBSD.ORG" <smp@FreeBSD.ORG>
Subject:   Re: per cpu runqueues, cpu affinity and cpu binding.
Message-ID:  <Pine.LNX.4.33L2.0107021319420.22067-100000@grace.speakeasy.net>
In-Reply-To: <Pine.BSF.4.21.0107021449340.13213-100000@InterJet.elischer.org>

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http://www.cs.washington.edu/research/smt/

http://www.cs.washington.edu/research/smt/papers/ieee_micro.pdf

http://www.bearcave.com/software/java/comp_links.html

Supposedly an upcomping XEON processor will have SMT / ILP. Not to prognosticate
but I think having TEUs (thread execution units) will be a very good idea (tm).
What about architectures where the CPUs might share the same L2/L3 cache?
Multichip modules or multiple on die cpus? IBM Power4?

Two procs, one L2.

http://www.eetimes.com/story/OEG19990804S0023

http://arstechnica.com/cpu/4q99/majc/majc-1.html

This is very probably most likely sorta in our near future.

Sean.



On Mon, 2 Jul 2001, Julian Elischer wrote:

>
>
> On Mon, 2 Jul 2001, Alfred Perlstein wrote:
>
> > * Julian Elischer <julian@elischer.org> [010702 14:58] wrote:
> > >
> > > If you select to run 2 thread carriers (see other mail on nomenclature)>
> > > (KSEs) then you have specifically asked for 2 processors worth of
> > > concurrency so we ASSUME you know what you are doing.. If you want to run
> > > all the threads on a single processor to get better cache activity, then
> > > you should't ASK to run on 2  (or more) processors.
> >
> > Agreed, however don't forget about the multiple thread execution
> > units that may become available, meaning that as long as you share
> > an address space you can run two (or more) threads in parrallel on
> > a single processor.  You wouldn't want to preclude us of taking
> > advantage of that if it becomes available.
>
> If that architecture takes off (I have my doubts.. ALPHA was the only one
> trying that), then we can change the rules about only allowing one thread
> container per processor (and limit it to the number of thread execution
> units).
>
>
>
>
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